From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Francesco Dolcini <francesco@dolcini.it>
Cc: Siddharth Vadapalli <s-vadapalli@ti.com>, <nm@ti.com>,
<vigneshr@ti.com>, <kristo@kernel.org>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <danishanwar@ti.com>,
<srk@ti.com>
Subject: Re: [PATCH v2 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes
Date: Wed, 22 May 2024 15:51:43 +0530 [thread overview]
Message-ID: <47146d6c-bab3-4089-8dd5-4d71762bba2c@ti.com> (raw)
In-Reply-To: <20240521200909.GA3707@francesco-nb>
On Tue, May 21, 2024 at 10:09:09PM +0200, Francesco Dolcini wrote:
> On Mon, May 20, 2024 at 03:41:47PM +0530, Siddharth Vadapalli wrote:
> > TI's J784S4 has two instances of Gen3 x4 Lane PCIe Controllers namely
> > PCIE0 and PCIE1. Add support for the Root Complex Mode of operation of
> > these PCIe instances.
>
> What about PCIE2? J784S4 has 3 PCIe instances, it would be beneficial to
> add all 3, not just the first twos.
Thank you for reviewing the patch. I agree that it was incorrect for me
to mention that J784S4 has two instances of PCIe. It actually has 4
instances as mentioned in the Excel Sheet provided along with the
Technical Reference Manual at:
https://www.ti.com/lit/zip/spruj52
namely PCIe0, PCIe1, PCIe2 and PCIe3.
Since the J784S4 EVM has only PCIe0 and PCIe1 instances of PCIe brought
out, I was able to test them and therefore added support for only those
two instances in this series. However I do agree that all 4 should be
added to the SoC file (k3-j784s4-main.dtsi) for the sake of completeness
in terms of describing the SoC, while the Board file (k3-j784s4-evm.dts)
can still contain just PCIe0 and PCIe1 as those are the ones brought out
on the board. I will implement your suggestion in the v3 series.
Regards,
Siddharth.
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WARNING: multiple messages have this Message-ID (diff)
From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Francesco Dolcini <francesco@dolcini.it>
Cc: Siddharth Vadapalli <s-vadapalli@ti.com>, <nm@ti.com>,
<vigneshr@ti.com>, <kristo@kernel.org>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <danishanwar@ti.com>,
<srk@ti.com>
Subject: Re: [PATCH v2 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes
Date: Wed, 22 May 2024 15:51:43 +0530 [thread overview]
Message-ID: <47146d6c-bab3-4089-8dd5-4d71762bba2c@ti.com> (raw)
In-Reply-To: <20240521200909.GA3707@francesco-nb>
On Tue, May 21, 2024 at 10:09:09PM +0200, Francesco Dolcini wrote:
> On Mon, May 20, 2024 at 03:41:47PM +0530, Siddharth Vadapalli wrote:
> > TI's J784S4 has two instances of Gen3 x4 Lane PCIe Controllers namely
> > PCIE0 and PCIE1. Add support for the Root Complex Mode of operation of
> > these PCIe instances.
>
> What about PCIE2? J784S4 has 3 PCIe instances, it would be beneficial to
> add all 3, not just the first twos.
Thank you for reviewing the patch. I agree that it was incorrect for me
to mention that J784S4 has two instances of PCIe. It actually has 4
instances as mentioned in the Excel Sheet provided along with the
Technical Reference Manual at:
https://www.ti.com/lit/zip/spruj52
namely PCIe0, PCIe1, PCIe2 and PCIe3.
Since the J784S4 EVM has only PCIe0 and PCIe1 instances of PCIe brought
out, I was able to test them and therefore added support for only those
two instances in this series. However I do agree that all 4 should be
added to the SoC file (k3-j784s4-main.dtsi) for the sake of completeness
in terms of describing the SoC, while the Board file (k3-j784s4-evm.dts)
can still contain just PCIe0 and PCIe1 as those are the ones brought out
on the board. I will implement your suggestion in the v3 series.
Regards,
Siddharth.
next prev parent reply other threads:[~2024-05-22 10:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-20 10:11 [PATCH v2 0/3] Add PCIe DT support for TI's J784S4 SoC Siddharth Vadapalli
2024-05-20 10:11 ` Siddharth Vadapalli
2024-05-20 10:11 ` [PATCH v2 1/3] arm64: dts: ti: k3-j784s4-main: Add PCIe nodes Siddharth Vadapalli
2024-05-20 10:11 ` Siddharth Vadapalli
2024-05-21 20:09 ` Francesco Dolcini
2024-05-21 20:09 ` Francesco Dolcini
2024-05-22 10:21 ` Siddharth Vadapalli [this message]
2024-05-22 10:21 ` Siddharth Vadapalli
2024-05-20 10:11 ` [PATCH v2 2/3] arm64: dts: ti: k3-j784s4-evm: Enable PCIe0 and PCIe1 in RC Mode Siddharth Vadapalli
2024-05-20 10:11 ` Siddharth Vadapalli
2024-05-20 10:11 ` [PATCH v2 3/3] arm64: dts: ti: k3-j784s4-evm: Add overlay for PCIe0 and PCIe1 EP Mode Siddharth Vadapalli
2024-05-20 10:11 ` Siddharth Vadapalli
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