* MPC8360: Support for two SDRAM banks in the Kernel memory management?
@ 2007-10-30 8:50 Jens Gehrlein
0 siblings, 0 replies; only message in thread
From: Jens Gehrlein @ 2007-10-30 8:50 UTC (permalink / raw)
To: linuxppc-embedded Mailinglist
Hi,
the MPC8360 has two DDR SDRAM controllers. In the 2x32 bit mode
data transfers from/to the SDRAM can be handled by the MPC and the
QUICC Engine independently. For instance, the core can access one
bank and the QUICC Engine can access the other bank via DMA for
lookup tables, temporary buffers, etc. in the same time.
IMHO the Linux Kernel supports only one linear virtual address space.
So how could the kernel memory management (DMA, alloc, etc.) ensure,
that data transfers go from/to the QUICC Engine to/from the second
SDRAM bank?
Does anybody know if bank-separated memory management is supported
by the Linux Kernel, especially for the MPC8360?
Thanks in advance
Jens
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2007-10-30 9:19 UTC | newest]
Thread overview: (only message) (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2007-10-30 8:50 MPC8360: Support for two SDRAM banks in the Kernel memory management? Jens Gehrlein
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.