Re: [Qemu-devel] [RFC][PATCH] fix sparc32 mxcc 64 bit read word order

[Robert Reif <reif@earthlink.net>]

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>
>
>This patch fixes the word order for 64 bit reads of the mxcc registers.
>  
>


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Index: target-sparc/op_helper.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.52
diff -p -u -r1.52 op_helper.c
--- target-sparc/op_helper.c	11 Nov 2007 19:46:09 -0000	1.52
+++ target-sparc/op_helper.c	15 Nov 2007 23:04:48 -0000
@@ -196,8 +196,8 @@ void helper_ld_asi(int asi, int size, in
         switch (T0) {
         case 0x01c00a00: /* MXCC control register */
             if (size == 8) {
-                ret = env->mxccregs[3];
-                T0 = env->mxccregs[3] >> 32;
+                ret = env->mxccregs[3] >> 32;
+                T0 = env->mxccregs[3];
             } else
                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
             break;
@@ -209,8 +209,8 @@ void helper_ld_asi(int asi, int size, in
             break;
         case 0x01c00f00: /* MBus port address register */
             if (size == 8) {
-                ret = env->mxccregs[7];
-                T0 = env->mxccregs[7] >> 32;
+                ret = env->mxccregs[7] >> 32;
+                T0 = env->mxccregs[7];
             } else
                 DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);
             break;