* [PATCH] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer
@ 2025-12-17 6:39 frank.chang
2025-12-18 13:05 ` Daniel Henrique Barboza
0 siblings, 1 reply; 3+ messages in thread
From: frank.chang @ 2025-12-17 6:39 UTC (permalink / raw)
To: qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs,
Frank Chang, Max Chou
From: Frank Chang <frank.chang@sifive.com>
Use designated initializers to initialize riscv_excp_names[] and
riscv_intr_names[] so that we don't have to explicitly add "reserved"
items.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
---
target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------
1 file changed, 45 insertions(+), 44 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index aa58ba8b99a..ee859093f78 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -305,60 +305,61 @@ const char * const riscv_rvv_regnames[] = {
};
static const char * const riscv_excp_names[] = {
- "misaligned_fetch",
- "fault_fetch",
- "illegal_instruction",
- "breakpoint",
- "misaligned_load",
- "fault_load",
- "misaligned_store",
- "fault_store",
- "user_ecall",
- "supervisor_ecall",
- "hypervisor_ecall",
- "machine_ecall",
- "exec_page_fault",
- "load_page_fault",
- "reserved",
- "store_page_fault",
- "double_trap",
- "reserved",
- "reserved",
- "reserved",
- "guest_exec_page_fault",
- "guest_load_page_fault",
- "reserved",
- "guest_store_page_fault",
+ [RISCV_EXCP_INST_ADDR_MIS] = "misaligned_fetch",
+ [RISCV_EXCP_INST_ACCESS_FAULT] = "fault_fetch",
+ [RISCV_EXCP_ILLEGAL_INST] = "illegal_instruction",
+ [RISCV_EXCP_BREAKPOINT] = "breakpoint",
+ [RISCV_EXCP_LOAD_ADDR_MIS] = "misaligned_load",
+ [RISCV_EXCP_LOAD_ACCESS_FAULT] = "fault_load",
+ [RISCV_EXCP_STORE_AMO_ADDR_MIS] = "misaligned_store",
+ [RISCV_EXCP_STORE_AMO_ACCESS_FAULT] = "fault_store",
+ [RISCV_EXCP_U_ECALL] = "user_ecall",
+ [RISCV_EXCP_S_ECALL] = "supervisor_ecall",
+ [RISCV_EXCP_VS_ECALL] = "hypervisor_ecall",
+ [RISCV_EXCP_M_ECALL] = "machine_ecall",
+ [RISCV_EXCP_INST_PAGE_FAULT] = "exec_page_fault",
+ [RISCV_EXCP_LOAD_PAGE_FAULT] = "load_page_fault",
+ [RISCV_EXCP_STORE_PAGE_FAULT] = "store_page_fault",
+ [RISCV_EXCP_DOUBLE_TRAP] = "double_trap",
+ [RISCV_EXCP_SW_CHECK] = "sw_check",
+ [RISCV_EXCP_HW_ERR] = "hw_error",
+ [RISCV_EXCP_INST_GUEST_PAGE_FAULT] = "guest_exec_page_fault",
+ [RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT] = "guest_load_page_fault",
+ [RISCV_EXCP_VIRT_INSTRUCTION_FAULT] = "virt_illegal_instruction",
+ [RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT] = "guest_store_page_fault",
+ [RISCV_EXCP_SEMIHOST] = "semihost",
};
static const char * const riscv_intr_names[] = {
- "u_software",
- "s_software",
- "vs_software",
- "m_software",
- "u_timer",
- "s_timer",
- "vs_timer",
- "m_timer",
- "u_external",
- "s_external",
- "vs_external",
- "m_external",
- "reserved",
- "reserved",
- "reserved",
- "reserved"
+ [IRQ_U_SOFT] = "u_software",
+ [IRQ_S_SOFT] = "s_software",
+ [IRQ_VS_SOFT] = "vs_software",
+ [IRQ_M_SOFT] = "m_software",
+ [IRQ_U_TIMER] = "u_timer",
+ [IRQ_S_TIMER] = "s_timer",
+ [IRQ_VS_TIMER] = "vs_timer",
+ [IRQ_M_TIMER] = "m_timer",
+ [IRQ_U_EXT] = "u_external",
+ [IRQ_S_EXT] = "s_external",
+ [IRQ_VS_EXT] = "vs_external",
+ [IRQ_M_EXT] = "m_external",
+ [IRQ_S_GEXT] = "s_guest_external",
+ [IRQ_PMU_OVF] = "counter_overflow",
};
const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
{
if (async) {
- return (cause < ARRAY_SIZE(riscv_intr_names)) ?
- riscv_intr_names[cause] : "(unknown)";
+ if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) {
+ return riscv_intr_names[cause];
+ }
} else {
- return (cause < ARRAY_SIZE(riscv_excp_names)) ?
- riscv_excp_names[cause] : "(unknown)";
+ if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) {
+ return riscv_excp_names[cause];
+ }
}
+
+ return "(unknown)";
}
void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer
2025-12-17 6:39 [PATCH] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer frank.chang
@ 2025-12-18 13:05 ` Daniel Henrique Barboza
2025-12-19 0:31 ` Frank Chang
0 siblings, 1 reply; 3+ messages in thread
From: Daniel Henrique Barboza @ 2025-12-18 13:05 UTC (permalink / raw)
To: frank.chang, qemu-devel
Cc: Palmer Dabbelt, Alistair Francis, Weiwei Li, Liu Zhiwei,
open list:RISC-V TCG CPUs, Max Chou
On 12/17/25 3:39 AM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Use designated initializers to initialize riscv_excp_names[] and
> riscv_intr_names[] so that we don't have to explicitly add "reserved"
> items.
You also added entries that were missing before in both arrays (sw_check,
hw_error, semihost, counter_overflow ...). Not sure if it's worth sending a
v2 just to amend the commit msg though.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Max Chou <max.chou@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------
> 1 file changed, 45 insertions(+), 44 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index aa58ba8b99a..ee859093f78 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -305,60 +305,61 @@ const char * const riscv_rvv_regnames[] = {
> };
>
> static const char * const riscv_excp_names[] = {
> - "misaligned_fetch",
> - "fault_fetch",
> - "illegal_instruction",
> - "breakpoint",
> - "misaligned_load",
> - "fault_load",
> - "misaligned_store",
> - "fault_store",
> - "user_ecall",
> - "supervisor_ecall",
> - "hypervisor_ecall",
> - "machine_ecall",
> - "exec_page_fault",
> - "load_page_fault",
> - "reserved",
> - "store_page_fault",
> - "double_trap",
> - "reserved",
> - "reserved",
> - "reserved",
> - "guest_exec_page_fault",
> - "guest_load_page_fault",
> - "reserved",
> - "guest_store_page_fault",
> + [RISCV_EXCP_INST_ADDR_MIS] = "misaligned_fetch",
> + [RISCV_EXCP_INST_ACCESS_FAULT] = "fault_fetch",
> + [RISCV_EXCP_ILLEGAL_INST] = "illegal_instruction",
> + [RISCV_EXCP_BREAKPOINT] = "breakpoint",
> + [RISCV_EXCP_LOAD_ADDR_MIS] = "misaligned_load",
> + [RISCV_EXCP_LOAD_ACCESS_FAULT] = "fault_load",
> + [RISCV_EXCP_STORE_AMO_ADDR_MIS] = "misaligned_store",
> + [RISCV_EXCP_STORE_AMO_ACCESS_FAULT] = "fault_store",
> + [RISCV_EXCP_U_ECALL] = "user_ecall",
> + [RISCV_EXCP_S_ECALL] = "supervisor_ecall",
> + [RISCV_EXCP_VS_ECALL] = "hypervisor_ecall",
> + [RISCV_EXCP_M_ECALL] = "machine_ecall",
> + [RISCV_EXCP_INST_PAGE_FAULT] = "exec_page_fault",
> + [RISCV_EXCP_LOAD_PAGE_FAULT] = "load_page_fault",
> + [RISCV_EXCP_STORE_PAGE_FAULT] = "store_page_fault",
> + [RISCV_EXCP_DOUBLE_TRAP] = "double_trap",
> + [RISCV_EXCP_SW_CHECK] = "sw_check",
> + [RISCV_EXCP_HW_ERR] = "hw_error",
> + [RISCV_EXCP_INST_GUEST_PAGE_FAULT] = "guest_exec_page_fault",
> + [RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT] = "guest_load_page_fault",
> + [RISCV_EXCP_VIRT_INSTRUCTION_FAULT] = "virt_illegal_instruction",
> + [RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT] = "guest_store_page_fault",
> + [RISCV_EXCP_SEMIHOST] = "semihost",
> };
>
> static const char * const riscv_intr_names[] = {
> - "u_software",
> - "s_software",
> - "vs_software",
> - "m_software",
> - "u_timer",
> - "s_timer",
> - "vs_timer",
> - "m_timer",
> - "u_external",
> - "s_external",
> - "vs_external",
> - "m_external",
> - "reserved",
> - "reserved",
> - "reserved",
> - "reserved"
> + [IRQ_U_SOFT] = "u_software",
> + [IRQ_S_SOFT] = "s_software",
> + [IRQ_VS_SOFT] = "vs_software",
> + [IRQ_M_SOFT] = "m_software",
> + [IRQ_U_TIMER] = "u_timer",
> + [IRQ_S_TIMER] = "s_timer",
> + [IRQ_VS_TIMER] = "vs_timer",
> + [IRQ_M_TIMER] = "m_timer",
> + [IRQ_U_EXT] = "u_external",
> + [IRQ_S_EXT] = "s_external",
> + [IRQ_VS_EXT] = "vs_external",
> + [IRQ_M_EXT] = "m_external",
> + [IRQ_S_GEXT] = "s_guest_external",
> + [IRQ_PMU_OVF] = "counter_overflow",
> };
>
> const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
> {
> if (async) {
> - return (cause < ARRAY_SIZE(riscv_intr_names)) ?
> - riscv_intr_names[cause] : "(unknown)";
> + if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) {
> + return riscv_intr_names[cause];
> + }
> } else {
> - return (cause < ARRAY_SIZE(riscv_excp_names)) ?
> - riscv_excp_names[cause] : "(unknown)";
> + if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) {
> + return riscv_excp_names[cause];
> + }
> }
> +
> + return "(unknown)";
> }
>
> void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer
2025-12-18 13:05 ` Daniel Henrique Barboza
@ 2025-12-19 0:31 ` Frank Chang
0 siblings, 0 replies; 3+ messages in thread
From: Frank Chang @ 2025-12-19 0:31 UTC (permalink / raw)
To: Daniel Henrique Barboza
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Weiwei Li,
Liu Zhiwei, open list:RISC-V TCG CPUs, Max Chou
[-- Attachment #1: Type: text/plain, Size: 5120 bytes --]
Hi Daniel,
On Thu, Dec 18, 2025 at 9:05 PM Daniel Henrique Barboza <
dbarboza@ventanamicro.com> wrote:
>
>
> On 12/17/25 3:39 AM, frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > Use designated initializers to initialize riscv_excp_names[] and
> > riscv_intr_names[] so that we don't have to explicitly add "reserved"
> > items.
>
> You also added entries that were missing before in both arrays (sw_check,
> hw_error, semihost, counter_overflow ...). Not sure if it's worth sending a
> v2 just to amend the commit msg though.
>
Sure, I can do that.
Regards,
Frank Chang
>
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > Reviewed-by: Max Chou <max.chou@sifive.com>
> > ---
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
>
> > target/riscv/cpu.c | 89 +++++++++++++++++++++++-----------------------
> > 1 file changed, 45 insertions(+), 44 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index aa58ba8b99a..ee859093f78 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -305,60 +305,61 @@ const char * const riscv_rvv_regnames[] = {
> > };
> >
> > static const char * const riscv_excp_names[] = {
> > - "misaligned_fetch",
> > - "fault_fetch",
> > - "illegal_instruction",
> > - "breakpoint",
> > - "misaligned_load",
> > - "fault_load",
> > - "misaligned_store",
> > - "fault_store",
> > - "user_ecall",
> > - "supervisor_ecall",
> > - "hypervisor_ecall",
> > - "machine_ecall",
> > - "exec_page_fault",
> > - "load_page_fault",
> > - "reserved",
> > - "store_page_fault",
> > - "double_trap",
> > - "reserved",
> > - "reserved",
> > - "reserved",
> > - "guest_exec_page_fault",
> > - "guest_load_page_fault",
> > - "reserved",
> > - "guest_store_page_fault",
> > + [RISCV_EXCP_INST_ADDR_MIS] = "misaligned_fetch",
> > + [RISCV_EXCP_INST_ACCESS_FAULT] = "fault_fetch",
> > + [RISCV_EXCP_ILLEGAL_INST] = "illegal_instruction",
> > + [RISCV_EXCP_BREAKPOINT] = "breakpoint",
> > + [RISCV_EXCP_LOAD_ADDR_MIS] = "misaligned_load",
> > + [RISCV_EXCP_LOAD_ACCESS_FAULT] = "fault_load",
> > + [RISCV_EXCP_STORE_AMO_ADDR_MIS] = "misaligned_store",
> > + [RISCV_EXCP_STORE_AMO_ACCESS_FAULT] = "fault_store",
> > + [RISCV_EXCP_U_ECALL] = "user_ecall",
> > + [RISCV_EXCP_S_ECALL] = "supervisor_ecall",
> > + [RISCV_EXCP_VS_ECALL] = "hypervisor_ecall",
> > + [RISCV_EXCP_M_ECALL] = "machine_ecall",
> > + [RISCV_EXCP_INST_PAGE_FAULT] = "exec_page_fault",
> > + [RISCV_EXCP_LOAD_PAGE_FAULT] = "load_page_fault",
> > + [RISCV_EXCP_STORE_PAGE_FAULT] = "store_page_fault",
> > + [RISCV_EXCP_DOUBLE_TRAP] = "double_trap",
> > + [RISCV_EXCP_SW_CHECK] = "sw_check",
> > + [RISCV_EXCP_HW_ERR] = "hw_error",
> > + [RISCV_EXCP_INST_GUEST_PAGE_FAULT] = "guest_exec_page_fault",
> > + [RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT] = "guest_load_page_fault",
> > + [RISCV_EXCP_VIRT_INSTRUCTION_FAULT] = "virt_illegal_instruction",
> > + [RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT] =
> "guest_store_page_fault",
> > + [RISCV_EXCP_SEMIHOST] = "semihost",
> > };
> >
> > static const char * const riscv_intr_names[] = {
> > - "u_software",
> > - "s_software",
> > - "vs_software",
> > - "m_software",
> > - "u_timer",
> > - "s_timer",
> > - "vs_timer",
> > - "m_timer",
> > - "u_external",
> > - "s_external",
> > - "vs_external",
> > - "m_external",
> > - "reserved",
> > - "reserved",
> > - "reserved",
> > - "reserved"
> > + [IRQ_U_SOFT] = "u_software",
> > + [IRQ_S_SOFT] = "s_software",
> > + [IRQ_VS_SOFT] = "vs_software",
> > + [IRQ_M_SOFT] = "m_software",
> > + [IRQ_U_TIMER] = "u_timer",
> > + [IRQ_S_TIMER] = "s_timer",
> > + [IRQ_VS_TIMER] = "vs_timer",
> > + [IRQ_M_TIMER] = "m_timer",
> > + [IRQ_U_EXT] = "u_external",
> > + [IRQ_S_EXT] = "s_external",
> > + [IRQ_VS_EXT] = "vs_external",
> > + [IRQ_M_EXT] = "m_external",
> > + [IRQ_S_GEXT] = "s_guest_external",
> > + [IRQ_PMU_OVF] = "counter_overflow",
> > };
> >
> > const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
> > {
> > if (async) {
> > - return (cause < ARRAY_SIZE(riscv_intr_names)) ?
> > - riscv_intr_names[cause] : "(unknown)";
> > + if ((cause < ARRAY_SIZE(riscv_intr_names)) &&
> riscv_intr_names[cause]) {
> > + return riscv_intr_names[cause];
> > + }
> > } else {
> > - return (cause < ARRAY_SIZE(riscv_excp_names)) ?
> > - riscv_excp_names[cause] : "(unknown)";
> > + if ((cause < ARRAY_SIZE(riscv_excp_names)) &&
> riscv_excp_names[cause]) {
> > + return riscv_excp_names[cause];
> > + }
> > }
> > +
> > + return "(unknown)";
> > }
> >
> > void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
>
>
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2025-12-17 6:39 [PATCH] target/riscv: Initialize riscv_excp_names[] and riscv_intr_names[] using designated initializer frank.chang
2025-12-18 13:05 ` Daniel Henrique Barboza
2025-12-19 0:31 ` Frank Chang
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