* [Qemu-devel] [PATCH] sparc32 mmu register fixes
@ 2008-02-11 0:28 Robert Reif
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From: Robert Reif @ 2008-02-11 0:28 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 102 bytes --]
This patch gets openboot prom mmu register self tests passing for lx,
ss4, ss5 and ss10 prom images.
[-- Attachment #2: mmu.diff.txt --]
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Index: target-sparc/cpu.h
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/cpu.h,v
retrieving revision 1.61
diff -p -u -r1.61 cpu.h
--- target-sparc/cpu.h 28 Nov 2007 20:54:33 -0000 1.61
+++ target-sparc/cpu.h 11 Feb 2008 00:07:10 -0000
@@ -198,6 +198,10 @@ typedef struct CPUSPARCState {
int interrupt_request;
int halted;
uint32_t mmu_bm;
+ uint32_t mmu_ctpr_mask;
+ uint32_t mmu_cxr_mask;
+ uint32_t mmu_sfsr_mask;
+ uint32_t mmu_trcr_mask;
/* NOTE: we allow 8 more registers to handle wrapping */
target_ulong regbase[NWINDOWS * 16 + 8];
Index: target-sparc/helper.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/helper.c,v
retrieving revision 1.33
diff -p -u -r1.33 helper.c
--- target-sparc/helper.c 25 Dec 2007 07:49:10 -0000 1.33
+++ target-sparc/helper.c 11 Feb 2008 00:07:11 -0000
@@ -129,7 +129,7 @@ int get_physical_address (CPUState *env,
/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
/* Context base + context number */
- pde_ptr = ((env->mmuregs[1] & ~63)<< 4) + (env->mmuregs[2] << 2);
+ pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
pde = ldl_phys(pde_ptr);
/* Ctx pde */
Index: target-sparc/op_helper.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.65
diff -p -u -r1.65 op_helper.c
--- target-sparc/op_helper.c 1 Jan 2008 17:07:39 -0000 1.65
+++ target-sparc/op_helper.c 11 Feb 2008 00:07:12 -0000
@@ -591,7 +591,7 @@ void helper_st_asi(int asi, int size)
oldreg = env->mmuregs[reg];
switch(reg) {
- case 0:
+ case 0: // Control Register
env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
(T1 & 0x00ffffff);
// Mappings generated during no-fault mode or MMU
@@ -600,21 +600,27 @@ void helper_st_asi(int asi, int size)
(env->mmuregs[reg] & (MMU_E | MMU_NF | env->mmu_bm)))
tlb_flush(env, 1);
break;
- case 2:
- env->mmuregs[reg] = T1;
+ case 1: // Context Table Pointer Register
+ env->mmuregs[reg] = T1 & env->mmu_ctpr_mask;
+ break;
+ case 2: // Context Register
+ env->mmuregs[reg] = T1 & env->mmu_cxr_mask;
if (oldreg != env->mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
tlb_flush(env, 1);
}
break;
- case 3:
- case 4:
+ case 3: // Synchronous Fault Status Register with Clear
+ case 4: // Synchronous Fault Address Register
+ break;
+ case 0x10: // TLB Replacement Control Register
+ env->mmuregs[reg] = T1 & env->mmu_trcr_mask;
break;
- case 0x13:
- env->mmuregs[3] = T1;
+ case 0x13: // Synchronous Fault Status Register with Read and Clear
+ env->mmuregs[3] = T1 & env->mmu_sfsr_mask;
break;
- case 0x14:
+ case 0x14: // Synchronous Fault Address Register
env->mmuregs[4] = T1;
break;
default:
Index: target-sparc/translate.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/translate.c,v
retrieving revision 1.86
diff -p -u -r1.86 translate.c
--- target-sparc/translate.c 1 Feb 2008 10:50:11 -0000 1.86
+++ target-sparc/translate.c 11 Feb 2008 00:07:14 -0000
@@ -62,6 +62,10 @@ struct sparc_def_t {
uint32_t fpu_version;
uint32_t mmu_version;
uint32_t mmu_bm;
+ uint32_t mmu_ctpr_mask;
+ uint32_t mmu_cxr_mask;
+ uint32_t mmu_sfsr_mask;
+ uint32_t mmu_trcr_mask;
};
static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
@@ -3758,6 +3762,10 @@ CPUSPARCState *cpu_sparc_init(const char
env->fsr = def->fpu_version;
#if !defined(TARGET_SPARC64)
env->mmu_bm = def->mmu_bm;
+ env->mmu_ctpr_mask = def->mmu_ctpr_mask;
+ env->mmu_cxr_mask = def->mmu_cxr_mask;
+ env->mmu_sfsr_mask = def->mmu_sfsr_mask;
+ env->mmu_trcr_mask = def->mmu_trcr_mask;
env->mmuregs[0] |= def->mmu_version;
cpu_sparc_set_id(env, 0);
#endif
@@ -3887,6 +3895,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Fujitsu MB86904",
@@ -3894,6 +3906,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x00ffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016fff,
+ .mmu_trcr_mask = 0x00ffffff,
},
{
.name = "Fujitsu MB86907",
@@ -3901,6 +3917,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016fff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "LSI L64811",
@@ -3908,6 +3928,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Cypress CY7C601",
@@ -3915,6 +3939,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Cypress CY7C611",
@@ -3922,6 +3950,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "TI SuperSparc II",
@@ -3929,6 +3961,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 0 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "TI MicroSparc I",
@@ -3936,6 +3972,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 4 << 17,
.mmu_version = 0x41000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0x00016fff,
+ .mmu_trcr_mask = 0x0000003f,
},
{
.name = "TI MicroSparc II",
@@ -3943,6 +3983,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 4 << 17,
.mmu_version = 0x02000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x00ffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016fff,
+ .mmu_trcr_mask = 0x00ffffff,
},
{
.name = "TI MicroSparc IIep",
@@ -3950,6 +3994,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 4 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x00ffffc0,
+ .mmu_cxr_mask = 0x000000ff,
+ .mmu_sfsr_mask = 0x00016bff,
+ .mmu_trcr_mask = 0x00ffffff,
},
{
.name = "TI SuperSparc 51",
@@ -3957,6 +4005,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 0 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "TI SuperSparc 61",
@@ -3964,6 +4016,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 0 << 17,
.mmu_version = 0x04000000,
.mmu_bm = 0x00002000,
+ .mmu_ctpr_mask = 0xffffffc0,
+ .mmu_cxr_mask = 0x0000ffff,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Ross RT625",
@@ -3971,6 +4027,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 1 << 17,
.mmu_version = 0x1e000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Ross RT620",
@@ -3978,6 +4038,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 1 << 17,
.mmu_version = 0x1f000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "BIT B5010",
@@ -3985,6 +4049,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
.mmu_version = 0x20000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Matsushita MN10501",
@@ -3992,6 +4060,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 0 << 17,
.mmu_version = 0x50000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "Weitek W8601",
@@ -3999,6 +4071,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
.mmu_version = 0x10 << 24,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "LEON2",
@@ -4006,6 +4082,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0xf2000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
{
.name = "LEON3",
@@ -4013,6 +4093,10 @@ static const sparc_def_t sparc_defs[] =
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
.mmu_version = 0xf3000000,
.mmu_bm = 0x00004000,
+ .mmu_ctpr_mask = 0x007ffff0,
+ .mmu_cxr_mask = 0x0000003f,
+ .mmu_sfsr_mask = 0xffffffff,
+ .mmu_trcr_mask = 0xffffffff,
},
#endif
};
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2008-02-11 0:28 [Qemu-devel] [PATCH] sparc32 mmu register fixes Robert Reif
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