[U-Boot-Users] [PATCH] Add Vitesse 8601 support to TSEC driver

[Andre Schwarz <andre.schwarz@matrix-vision.de>]

Tor,

after investigating the tsec code I'm wondering how your PHY  works in 
RGMII mode ...

I think that there are some things missing, e.g. taking RGMII into 
account during tsec_init.

/* Init ECNTRL */
        regs->ecntrl = ECNTRL_INIT_SETTINGS;

This will clear bit 27 which indicates RGMII as set up by the HRCW.


I would expect something like

        if ( priv->flags & TSEC_REDUCED )
                regs->ecntrl |= ECNTRL_RPM;

afterwards.



Before I'll start doing double work again : Have you some unposted 
patches regarding RGMII on TSEC ?

Am I missing something ?


@Kim : Did you ever run a MPC834x with a RGMII  PHY ? Is it known to work ?


regards,
Andre



Tor Krill schrieb:
> Add phy_info for Vitesse VSC8601.
> Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.
>
> Signed-off-by: Tor Krill <tor@excito.com>
> ---
>  drivers/net/tsec.c |   30 ++++++++++++++++++++++++++++++
>  drivers/net/tsec.h |    5 +++++
>  2 files changed, 35 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
> index 431a8d2..9d22aa3 100644
> --- a/drivers/net/tsec.c
> +++ b/drivers/net/tsec.c
> @@ -1267,6 +1267,35 @@ struct phy_info phy_info_VSC8244 = {
>  			   },
>  };
>  
> +struct phy_info phy_info_VSC8601 = {
> +		0x00007042,
> +		"Vitesse VSC8601",
> +		4,
> +		(struct phy_cmd[]){     /* config */
> +				/* Override PHY config settings */
> +				/* Configure some basic stuff */
> +				{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
> +#ifdef CFG_VSC8601_SKEWFIX
> +				{MIIM_VSC8601_EPHY_CON,MIIM_VSC8601_EPHY_CON_INIT_SKEW,NULL},
> +#endif
> +				{miim_end,}
> +				 },
> +		(struct phy_cmd[]){     /* startup */
> +				/* Read the Status (2x to make sure link is right) */
> +				{MIIM_STATUS, miim_read, NULL},
> +				/* Auto-negotiate */
> +				{MIIM_STATUS, miim_read, &mii_parse_sr},
> +				/* Read the status */
> +				{MIIM_VSC8244_AUX_CONSTAT, miim_read,
> +						&mii_parse_vsc8244},
> +				{miim_end,}
> +				},
> +		(struct phy_cmd[]){     /* shutdown */
> +				{miim_end,}
> +				},
> +};
> +
> +
>  struct phy_info phy_info_dm9161 = {
>  	0x0181b88,
>  	"Davicom DM9161E",
> @@ -1462,6 +1491,7 @@ struct phy_info *phy_info[] = {
>  	&phy_info_dm9161,
>  	&phy_info_lxt971,
>  	&phy_info_VSC8244,
> +	&phy_info_VSC8601,
>  	&phy_info_dp83865,
>  	&phy_info_rtl8211b,
>  	&phy_info_generic,
> diff --git a/drivers/net/tsec.h b/drivers/net/tsec.h
> index d4dc15a..cfa7d1a 100644
> --- a/drivers/net/tsec.h
> +++ b/drivers/net/tsec.h
> @@ -159,6 +159,11 @@
>  #define MIIM_VSC8244_LED_CON            0x1b
>  #define MIIM_VSC8244_LEDCON_INIT        0xF011
>  
> +/* Entry for Vitesse VSC8601 regs starts here (Not complete) */
> +/* Vitesse VSC8601 Extended PHY Control Register 1 */
> +#define MIIM_VSC8601_EPHY_CON			0x17
> +#define MIIM_VSC8601_EPHY_CON_INIT_SKEW	0x1120
> +
>  /* 88E1011 PHY Status Register */
>  #define MIIM_88E1011_PHY_STATUS         0x11
>  #define MIIM_88E1011_PHYSTAT_SPEED      0xc000
>   


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