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From: Andre Schwarz <andre.schwarz@matrix-vision.de>
To: u-boot@lists.denx.de
Subject: [U-Boot-Users] [PATCH] Add Vitesse 8601 support to TSEC driver
Date: Tue, 01 Apr 2008 16:35:29 +0200	[thread overview]
Message-ID: <47F24831.5060001@matrix-vision.de> (raw)
In-Reply-To: <2acbd3e40804010725w62947a2eofc20ec7b6dc77459@mail.gmail.com>

Andy Fleming schrieb:
> On Tue, Apr 1, 2008 at 9:08 AM, Andre Schwarz
> <andre.schwarz@matrix-vision.de> wrote:
>   
>>  Tor,
>>
>>  after investigating the tsec code I'm wondering how your PHY works in
>>  RGMII mode ...
>>
>>  I think that there are some things missing, e.g. taking RGMII into
>>  account during tsec_init.
>>
>>  /* Init ECNTRL */
>>  regs->ecntrl = ECNTRL_INIT_SETTINGS;
>>
>>  If you look carefully, you'll notice that ecntrl's RPM bit is
>> read-only. Those bits are configured by POR pin strappings.
>>
>>
>>  sorry, my documentation (MPC8349EARM rev.1) declares this register
>> read-write.
>>  Of course it will be configured by the HRCW but can be overwritten
>> afterwards.
>>
>>  If this is not true it's a documentation bug.
>>     
>
>
> Thank you for bringing this to my attention.  It is almost certainly a
> bug.  If you look at the 8349ERM (rather than the 8349EARM), you'll
> see that the bits are read-only (except for R100, which tsec.c does
> modify based on the link type).  I will file a bug with the docs
> people.
>
>
>   
I've x-checked and printed the register after init.
You're right - it's read only and the RPM bit is set.
But the ECNTL  register description @ 15.5.3.1.4 says "read/write" to 
all bits ...
>>  You may be more familiar with the UEC, which doesn't automatically
>> detect the link type, but is otherwise fairly similar to the tsec.
>>
>>
>>  What do you mean ?
>>  I'm trying to get two VSC8601 RGMII PHYs running on a MPC8343B ...
>>     
>
> sorry, I forgot which ethernet controller you were using, and I'm not
> as familiar with the 83xx family as the 85xx family.  Some of our
> parts have the QUICC Engine, which has an ethernet controller with
> some similar registers to the TSEC's.  I was guessing that was why you
> thought those bits were writable, rather than a documentation bug, but
> clearly I was wrong.  :)
>
>   
no problem.

Andre
> Andy
>
> Andy
>   



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  reply	other threads:[~2008-04-01 14:35 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2008-03-28 14:29 [U-Boot-Users] [PATCH] Add Vitesse 8601 support to TSEC driver Tor Krill
2008-03-28 21:33 ` André Schwarz
2008-03-31  6:33 ` Tor Krill
2008-03-31 14:04   ` Ben Warren
2008-03-31 14:01 ` Ben Warren
2008-03-31 18:18   ` Kim Phillips
2008-04-01 11:38     ` Andre Schwarz
2008-04-17 18:32     ` Andre Schwarz
2008-04-18  8:40       ` Tor Krill
2008-04-24 14:23         ` Andre Schwarz
2008-04-01 13:33 ` Andre Schwarz
2008-04-01 13:42   ` Andy Fleming
2008-04-01 14:08     ` Andre Schwarz
2008-04-01 14:25       ` Andy Fleming
2008-04-01 14:35         ` Andre Schwarz [this message]
2008-04-01 16:12   ` Kim Phillips
2008-04-02  8:01     ` André Schwarz

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