[U-Boot-Users] PPC440EPx/sequoia TLB question...

[Dave Littell <littelld@verizon.net>]

Stefan Roese wrote:
> On Wednesday 23 April 2008, Dave Littell wrote:
>> >From ?/board/amcc/sequoia/init.S:
>>
>> /* TLB-entry for Internal Registers & OCM */
>> tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
>>
>> Why is this memory region not marked Guarded?  It would seem to meet the
>> definition of ?non-well-behaved?.
> 
> Why do you think this is the case?
> 

Hi again, Stefan!

Well, there's registers in that address space, not unlike other
registers in other TLB entries (PCI, BCSR, etc.) that are marked
Guarded.  I would think the same rationale would apply to the internal
registers.

I need to go back and check the register settings for speculative
accesses.  I seem to remember that there's a 440EPx Errata (actually,
more than one) that has a workaround that turns off speculative
instruction fetches.  Data speculative accesses may have gotten squashed
in there as well, so it wouldn't matter what the TLB said if that's the
case.

>> Also the TLB entry for SDRAM marks it Guarded, but that?s one area I
>> would think wouldn't need to be Guarded.
> 
> This could be a mistake. Should work without G bis set too. Please give it a 
> try and send a patch to fix it, if it works fine.
> 

Hard to define "works fine" - this is the same 440EPx platform I'm
asking about over in the embedded Linux mailing list.  I'm pretty sure
the kernel doesn't flag SDRAM as Guarded, but I'll give it a try to see
how it goes.


Thanks,
Dave