[Qemu-devel] ESP: fix CFG2 register

[Qemu-devel] ESP: fix CFG2 register

[Hervé Poussineau]

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Hi,

In ESP SCSI adapter, all bits of CFG2 register should be writable. 
Exception is that bits 7 and 6 can only be reset by an adapter reset.
Attached patch implements this behaviour.

Hervé

[-- Attachment #2: esp_cfg2.diff --]
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Index: hw/esp.c
===================================================================
--- hw/esp.c	(revision 4252)
+++ hw/esp.c	(working copy)
@@ -139,7 +139,11 @@
 
 #define CFG1_RESREPT 0x40
 
-#define CFG2_MASK 0x15
+enum {
+    CFG2_S2FE = 0x08, /* SCSI-2 Features Enable */
+    CFG2_LSP  = 0x40, /* Latch SCSI Phase */
+    CFG2_DAE  = 0x80, /* Data Alignment Enable */
+};
 
 #define TCHI_FAS100A 0x4
 
@@ -202,6 +206,8 @@
     int32_t datalen;
     int lun;
 
+    /* XXX: Check if SCSI-2 commands are enabled (CFG2_S2FE) */
+
     DPRINTF("do_cmd: busid 0x%x\n", buf[0]);
     lun = buf[0] & 7;
     datalen = s->current_dev->send_command(s->current_dev, 0, &buf[1], lun);
@@ -548,7 +554,8 @@
     case ESP_WCCF ... ESP_WTEST:
         break;
     case ESP_CFG2:
-        s->rregs[saddr] = val & CFG2_MASK;
+        /* CFG2_DAE and CFG2_LSP can't be reset */
+        s->rregs[saddr] = val | (s->rregs[saddr] & (CFG2_DAE | CFG2_LSP));
         break;
     case ESP_CFG3 ... ESP_RES4:
         s->rregs[saddr] = val;