From: Heiko Stuebner <heiko@sntech.de>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org
Cc: Anup Patel <apatel@ventanamicro.com>,
Arnd Bergmann <arnd@arndb.de>, Anup Patel <anup@brainfault.org>,
linux-kernel@vger.kernel.org,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Atish Patra <atishp@atishpatra.org>,
linux-riscv@lists.infradead.org,
Nikita Shubin <n.shubin@yadro.com>,
Anup Patel <apatel@ventanamicro.com>
Subject: Re: [PATCH v2] RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output
Date: Tue, 11 Oct 2022 09:59:50 +0200 [thread overview]
Message-ID: <4820619.CvnuH1ECHv@phil> (raw)
In-Reply-To: <20220727043829.151794-1-apatel@ventanamicro.com>
Am Mittwoch, 27. Juli 2022, 06:38:29 CEST schrieb Anup Patel:
> Identifying the underlying RISC-V implementation can be important
> for some of the user space applications. For example, the perf tool
> uses arch specific CPU implementation id (i.e. CPUID) to select a
> JSON file describing custom perf events on a CPU.
>
> Currently, there is no way to identify RISC-V implementation so we
> add mvendorid, marchid, and mimpid to /proc/cpuinfo output.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> Tested-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
[on Qemu and Allwinner D1]
Tested-by: Heiko Stuebner <heiko@sntech.de>
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WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org
Cc: Anup Patel <apatel@ventanamicro.com>,
Arnd Bergmann <arnd@arndb.de>, Anup Patel <anup@brainfault.org>,
linux-kernel@vger.kernel.org,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Atish Patra <atishp@atishpatra.org>,
linux-riscv@lists.infradead.org,
Nikita Shubin <n.shubin@yadro.com>,
Anup Patel <apatel@ventanamicro.com>
Subject: Re: [PATCH v2] RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output
Date: Tue, 11 Oct 2022 09:59:50 +0200 [thread overview]
Message-ID: <4820619.CvnuH1ECHv@phil> (raw)
In-Reply-To: <20220727043829.151794-1-apatel@ventanamicro.com>
Am Mittwoch, 27. Juli 2022, 06:38:29 CEST schrieb Anup Patel:
> Identifying the underlying RISC-V implementation can be important
> for some of the user space applications. For example, the perf tool
> uses arch specific CPU implementation id (i.e. CPUID) to select a
> JSON file describing custom perf events on a CPU.
>
> Currently, there is no way to identify RISC-V implementation so we
> add mvendorid, marchid, and mimpid to /proc/cpuinfo output.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> Tested-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
[on Qemu and Allwinner D1]
Tested-by: Heiko Stuebner <heiko@sntech.de>
next prev parent reply other threads:[~2022-10-11 8:00 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-27 4:38 [PATCH v2] RISC-V: Add mvendorid, marchid, and mimpid to /proc/cpuinfo output Anup Patel
2022-07-27 4:38 ` Anup Patel
2022-07-27 8:31 ` Conor.Dooley
2022-07-27 8:31 ` Conor.Dooley
2022-07-27 8:55 ` Ben Dooks
2022-07-27 8:55 ` Ben Dooks
2022-07-27 10:06 ` Anup Patel
2022-07-27 10:06 ` Anup Patel
2022-07-27 10:12 ` Ben Dooks
2022-07-27 10:12 ` Ben Dooks
2022-07-27 11:53 ` Anup Patel
2022-07-27 11:53 ` Anup Patel
2022-08-11 5:05 ` Anup Patel
2022-08-11 5:05 ` Anup Patel
2022-10-04 2:54 ` Palmer Dabbelt
2022-10-04 2:54 ` Palmer Dabbelt
2022-10-04 3:44 ` Anup Patel
2022-10-04 3:44 ` Anup Patel
2022-10-04 4:35 ` Palmer Dabbelt
2022-10-04 4:35 ` Palmer Dabbelt
2022-10-13 21:25 ` Palmer Dabbelt
2022-10-13 21:25 ` Palmer Dabbelt
2022-10-04 4:30 ` Anup Patel
2022-10-04 4:30 ` Anup Patel
2022-10-11 7:59 ` Heiko Stuebner [this message]
2022-10-11 7:59 ` Heiko Stuebner
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