[lm-sensors] [PATCH 2/2] hwmon (hwmon-vid): add 6-bit vid codes for

[lm-sensors] [PATCH 2/2] hwmon (hwmon-vid): add 6-bit vid codes for

[Frank Myhr]

AMD NPT 0Fh cpus use 6 bit VID codes. Successive codes with msb 0
describe 25mV decrements, while those with msb 1 describe 12.5mV decrements.
Existing hwmon-vid.c is correct only for codes with msb 0; this patch adds
support for the codes with msb 1.

Ref:
p 309, Table 71
AMD Publication 32559, BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf

Signed-off-by: Frank Myhr <fmyhr@fhmtech.com>
---

--- linux-2.6.26-rc5_before/drivers/hwmon/hwmon-vid.c   2008-06-11 18:09:26.000000000 -0400
+++ linux-2.6.26-rc5_after/drivers/hwmon/hwmon-vid.c    2008-06-11 18:35:55.000000000 -0400
@@ -37,17 +37,26 @@
  * For VRD 10.0 and up, "VRD x.y Design Guide",
  * available at http://developer.intel.com/.
  *
+ * AMD NPT 0Fh (Athlon64 & Opteron), AMD Publication 32559,
+ * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
  * AMD Opteron processors don't follow the Intel specifications.
  * I'm going to "make up" 2.4 as the spec number for the Opterons.
  * No good reason just a mnemonic for the 24x Opteron processor
  * series.
  *
- * Opteron VID encoding is:
- *    00000  =  1.550 V
- *    00001  =  1.525 V
- *     . . . .
- *    11110  =  0.800 V
- *    11111  =  0.000 V (off)
+ * AMD NPT 0Fh VID encoding is:
+ *     VID[5:0]    Voltage [V]  Delta [mV]
+ *     --------    -----------  ---------
+ *     00 0000         1.550
+ *     00 0001         1.525   -25
+ *     . . . .
+ *     01 1110         0.800
+ *     01 1111         0.775   -25
+ *     10 0000         0.7625  -12.5
+ *     10 0001         0.7500  -12.5
+ *     . . . .
+ *     11 1110         0.3875
+ *     11 1111         0.3750  -12.5
  *
  * The 17 specification is in fact Intel Mobile Voltage Positioning -
  * (IMVP-II). You can find more information in the datasheet of Max1718
@@ -98,9 +107,11 @@ int vid_from_reg(int val, u8 vrm)
                if (val < 0x02 || val > 0xb2)
                        return 0;
                return((1600000 - (val - 2) * 6250 + 500) / 1000);
-       case 24:                /* Opteron processor */
-               val &= 0x1f;
-               return(val = 0x1f ? 0 : 1550 - val * 25);
+
+       case 24:                /* AMD NPT 0Fh (Athlon64 & Opteron) */
+               val &= 0x3f;
+               return((val < 32) ? 1550 - 25 * val
+                       : 775 - (25 * (val - 31)) / 2);

        case 91:                /* VRM 9.1 */
        case 90:                /* VRM 9.0 */


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Re: [lm-sensors] [PATCH 2/2] hwmon (hwmon-vid): add 6-bit vid codes

[Jean Delvare]

Hi Frank,

On Wed, 11 Jun 2008 22:45:02 -0400, Frank Myhr wrote:
> AMD NPT 0Fh cpus use 6 bit VID codes. Successive codes with msb 0
> describe 25mV decrements, while those with msb 1 describe 12.5mV decrements.
> Existing hwmon-vid.c is correct only for codes with msb 0; this patch adds
> support for the codes with msb 1.
> 
> Ref:
> p 309, Table 71
> AMD Publication 32559, BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors
> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf

Ah, excellent. I didn't know there was a public specification for the
Opteron VID encoding. And I didn't know that these were 6-bit VID
codes. Thanks for the pointer :)

> 
> Signed-off-by: Frank Myhr <fmyhr@fhmtech.com>
> ---
> 
> --- linux-2.6.26-rc5_before/drivers/hwmon/hwmon-vid.c   2008-06-11 18:09:26.000000000 -0400
> +++ linux-2.6.26-rc5_after/drivers/hwmon/hwmon-vid.c    2008-06-11 18:35:55.000000000 -0400
> @@ -37,17 +37,26 @@
>   * For VRD 10.0 and up, "VRD x.y Design Guide",
>   * available at http://developer.intel.com/.
>   *
> + * AMD NPT 0Fh (Athlon64 & Opteron), AMD Publication 32559,
> + * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf

Might be a good idea to mention the name and number of the relevant
table? I'd expect these to be stable across document updates (unlike
the page number).

>   * AMD Opteron processors don't follow the Intel specifications.
>   * I'm going to "make up" 2.4 as the spec number for the Opterons.
>   * No good reason just a mnemonic for the 24x Opteron processor
>   * series.
>   *
> - * Opteron VID encoding is:
> - *    00000  =  1.550 V
> - *    00001  =  1.525 V
> - *     . . . .
> - *    11110  =  0.800 V
> - *    11111  =  0.000 V (off)
> + * AMD NPT 0Fh VID encoding is:
> + *     VID[5:0]    Voltage [V]  Delta [mV]
> + *     --------    -----------  ---------
> + *     00 0000         1.550
> + *     00 0001         1.525   -25
> + *     . . . .
> + *     01 1110         0.800
> + *     01 1111         0.775   -25
> + *     10 0000         0.7625  -12.5
> + *     10 0001         0.7500  -12.5
> + *     . . . .
> + *     11 1110         0.3875
> + *     11 1111         0.3750  -12.5

I don't think there's much point in duplicating the table which you
already referenced. It was there before only due to the lack of
reference document.

>   *
>   * The 17 specification is in fact Intel Mobile Voltage Positioning -
>   * (IMVP-II). You can find more information in the datasheet of Max1718
> @@ -98,9 +107,11 @@ int vid_from_reg(int val, u8 vrm)
>                 if (val < 0x02 || val > 0xb2)
>                         return 0;

Eeek. Your mailer converted all tabs to spaces, so you patch doesn't
apply. Please correct and resubmit.

>                 return((1600000 - (val - 2) * 6250 + 500) / 1000);
> -       case 24:                /* Opteron processor */
> -               val &= 0x1f;
> -               return(val = 0x1f ? 0 : 1550 - val * 25);
> +
> +       case 24:                /* AMD NPT 0Fh (Athlon64 & Opteron) */
> +               val &= 0x3f;
> +               return((val < 32) ? 1550 - 25 * val

Note that return is not a function, so it doesn't need parentheses
(scripts/checkpatch.pl should have told you.)

> +                       : 775 - (25 * (val - 31)) / 2);
> 
>         case 91:                /* VRM 9.1 */
>         case 90:                /* VRM 9.0 */

-- 
Jean Delvare

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Re: [lm-sensors] [PATCH 2/2] hwmon (hwmon-vid): add 6-bit vid codes

[Frank Myhr]

Jean,

Thanks for your comments. Sorry for my slow response, I was on vacation and
then have been getting my head around quilt. Anyway, I think the below patch
fixes the problems you noticed.

Signed-off-by: Frank Myhr <fmyhr@fhmtech.com>
---

Index: linux/drivers/hwmon/hwmon-vid.c
=================================--- linux.orig/drivers/hwmon/hwmon-vid.c	2008-06-23 10:27:37.000000000 -0400
+++ linux/drivers/hwmon/hwmon-vid.c	2008-06-23 11:29:35.000000000 -0400
@@ -37,18 +37,14 @@
  * For VRD 10.0 and up, "VRD x.y Design Guide",
  * available at http://developer.intel.com/.
  *
+ * AMD NPT 0Fh (Athlon64 & Opteron), AMD Publication 32559,
+ * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
+ * Table 71. VID Code Voltages
  * AMD Opteron processors don't follow the Intel specifications.
  * I'm going to "make up" 2.4 as the spec number for the Opterons.
  * No good reason just a mnemonic for the 24x Opteron processor
  * series.
  *
- * Opteron VID encoding is:
- *    00000  =  1.550 V
- *    00001  =  1.525 V
- *     . . . .
- *    11110  =  0.800 V
- *    11111  =  0.000 V (off)
- *
  * The 17 specification is in fact Intel Mobile Voltage Positioning -
  * (IMVP-II). You can find more information in the datasheet of Max1718
  * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
@@ -98,9 +94,11 @@
 		if (val < 0x02 || val > 0xb2)
 			return 0;
 		return((1600000 - (val - 2) * 6250 + 500) / 1000);
-	case 24:                /* Opteron processor */
-		val &= 0x1f;
-		return(val = 0x1f ? 0 : 1550 - val * 25);
+
+	case 24:		/* AMD NPT 0Fh (Athlon64 & Opteron) */
+		val &= 0x3f;
+		return (val < 32) ? 1550 - 25 * val
+			: 775 - (25 * (val - 31)) / 2;

 	case 91:		/* VRM 9.1 */
 	case 90:		/* VRM 9.0 */

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Re: [lm-sensors] [PATCH 2/2] hwmon (hwmon-vid): add 6-bit vid codes

[Jean Delvare]

On Mon, 23 Jun 2008 12:06:26 -0400, Frank Myhr wrote:
> Jean,
> 
> Thanks for your comments. Sorry for my slow response, I was on vacation and
> then have been getting my head around quilt. Anyway, I think the below patch
> fixes the problems you noticed.

Time well spent, I'd say. quilt rocks.

> Signed-off-by: Frank Myhr <fmyhr@fhmtech.com>
> ---
> 
> Index: linux/drivers/hwmon/hwmon-vid.c
> =================================> --- linux.orig/drivers/hwmon/hwmon-vid.c	2008-06-23 10:27:37.000000000 -0400
> +++ linux/drivers/hwmon/hwmon-vid.c	2008-06-23 11:29:35.000000000 -0400
> @@ -37,18 +37,14 @@
>   * For VRD 10.0 and up, "VRD x.y Design Guide",
>   * available at http://developer.intel.com/.
>   *
> + * AMD NPT 0Fh (Athlon64 & Opteron), AMD Publication 32559,
> + * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
> + * Table 71. VID Code Voltages
>   * AMD Opteron processors don't follow the Intel specifications.
>   * I'm going to "make up" 2.4 as the spec number for the Opterons.
>   * No good reason just a mnemonic for the 24x Opteron processor
>   * series.
>   *
> - * Opteron VID encoding is:
> - *    00000  =  1.550 V
> - *    00001  =  1.525 V
> - *     . . . .
> - *    11110  =  0.800 V
> - *    11111  =  0.000 V (off)
> - *
>   * The 17 specification is in fact Intel Mobile Voltage Positioning -
>   * (IMVP-II). You can find more information in the datasheet of Max1718
>   * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
> @@ -98,9 +94,11 @@
>  		if (val < 0x02 || val > 0xb2)
>  			return 0;
>  		return((1600000 - (val - 2) * 6250 + 500) / 1000);
> -	case 24:                /* Opteron processor */
> -		val &= 0x1f;
> -		return(val = 0x1f ? 0 : 1550 - val * 25);
> +
> +	case 24:		/* AMD NPT 0Fh (Athlon64 & Opteron) */
> +		val &= 0x3f;
> +		return (val < 32) ? 1550 - 25 * val
> +			: 775 - (25 * (val - 31)) / 2;
> 
>  	case 91:		/* VRM 9.1 */
>  	case 90:		/* VRM 9.0 */

Looks good to me:

Acked-by: Jean Delvare <khali@linux-fr.org>

-- 
Jean Delvare

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Re: [lm-sensors] [PATCH 2/2] hwmon (hwmon-vid): add 6-bit vid codes

[Jean Delvare]

Hi Frank,

On Mon, 23 Jun 2008 18:18:50 +0200, Jean Delvare wrote:
> On Mon, 23 Jun 2008 12:06:26 -0400, Frank Myhr wrote:
> > Jean,
> > 
> > Thanks for your comments. Sorry for my slow response, I was on vacation and
> > then have been getting my head around quilt. Anyway, I think the below patch
> > fixes the problems you noticed.
> 
> Time well spent, I'd say. quilt rocks.
> 
> > Signed-off-by: Frank Myhr <fmyhr@fhmtech.com>
> > ---
> > 
> > Index: linux/drivers/hwmon/hwmon-vid.c
> > =================================> > --- linux.orig/drivers/hwmon/hwmon-vid.c	2008-06-23 10:27:37.000000000 -0400
> > +++ linux/drivers/hwmon/hwmon-vid.c	2008-06-23 11:29:35.000000000 -0400
> > @@ -37,18 +37,14 @@
> >   * For VRD 10.0 and up, "VRD x.y Design Guide",
> >   * available at http://developer.intel.com/.
> >   *
> > + * AMD NPT 0Fh (Athlon64 & Opteron), AMD Publication 32559,
> > + * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
> > + * Table 71. VID Code Voltages
> >   * AMD Opteron processors don't follow the Intel specifications.
> >   * I'm going to "make up" 2.4 as the spec number for the Opterons.
> >   * No good reason just a mnemonic for the 24x Opteron processor
> >   * series.
> >   *
> > - * Opteron VID encoding is:
> > - *    00000  =  1.550 V
> > - *    00001  =  1.525 V
> > - *     . . . .
> > - *    11110  =  0.800 V
> > - *    11111  =  0.000 V (off)
> > - *
> >   * The 17 specification is in fact Intel Mobile Voltage Positioning -
> >   * (IMVP-II). You can find more information in the datasheet of Max1718
> >   * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452
> > @@ -98,9 +94,11 @@
> >  		if (val < 0x02 || val > 0xb2)
> >  			return 0;
> >  		return((1600000 - (val - 2) * 6250 + 500) / 1000);
> > -	case 24:                /* Opteron processor */
> > -		val &= 0x1f;
> > -		return(val = 0x1f ? 0 : 1550 - val * 25);
> > +
> > +	case 24:		/* AMD NPT 0Fh (Athlon64 & Opteron) */
> > +		val &= 0x3f;
> > +		return (val < 32) ? 1550 - 25 * val
> > +			: 775 - (25 * (val - 31)) / 2;
> > 
> >  	case 91:		/* VRM 9.1 */
> >  	case 90:		/* VRM 9.0 */
> 
> Looks good to me:
> 
> Acked-by: Jean Delvare <khali@linux-fr.org>

FYI, a bug has been reported, which is most certainly caused by this
patch:
  http://bugzilla.kernel.org/show_bug.cgi?id\x11329

I am waiting for additional information from the reporter. At this
point, I suspect that older CPU models only have 5 VID pins and only
newer CPU models have 6 VID pins. In that case we would need a
different "vrm" value to differentiate between old and new models.

-- 
Jean Delvare

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Re: [lm-sensors] [PATCH 2/2] hwmon (hwmon-vid): add 6-bit vid codes

[Frank Myhr]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="windows-1252", Size: 4994 bytes --]

Hi Jean,

Thanks for the heads up. And even more for your patch, which I see has been
tested and accepted. It looks good to me.

I spent a long time looking for K8 specifications (cpuid and vid pins). AMD
doesn't make it easy--a big raspberry to them for not publishing "functional
data sheets" for any their sockets since 939. I think it would be helpful to
include some references to relevant cpu info in hwmon-vid (.c or doc). You
probably have a good reference to so quickly find the 0x2F (extended) model
cutoff for 5-vid-pin K8's.

I finally arrived at the same cutoff value using a variety of references and
combining Tables 2 and 3 below to get:

Table 1. K8 extended model <-> vid pin count

extended model	revision	vid pin count
--------------	-------------	-------------
   <= 0x2F	<= 90nm Rev E	5
0x30 - 0x3F	exist?		N/A ?
   >= 0x40	>= 90nm Rev F	6


== K8 Sockets =
Socket 940 (April 2003):
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31412.pdf
p. 35
5 VID pins
http://www.cpu-world.com/Sockets/Socket%20940.html


Socket 754 (September 2003):
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31410.pdf
p. 48
5 VID pins


Socket 939 (June 2004):
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31411.pdf
p. 39
5 VID pins


Socket AM2 (May 2006):
http://en.wikipedia.org/wiki/Socket_AM2
'"AM2 Processor Functional Data Sheet" (AMD document number 31117) has not been
made publicly available.'

6 VID pins shown in this unofficial image
http://www.techimo.com/forum/attachments/processors-memory-overclocking/19001d1201825486-pinout-volt-mod-socket-am2-untitled.gif
http://www.techimo.com/forum/processors-memory-overclocking/199420-pinout-volt-mod-socket-am2.html


Socket S1 (May 2006):
http://en.wikipedia.org/wiki/Socket_S1
'"Socket S1g1 Processor Functional Data Sheet" (AMD document number 31731) has
not been made publicly available.'


Socket F (August 2006):
http://en.wikipedia.org/wiki/Socket_F
'"Socket F (1207) Processor Functional Data Sheet" (AMD document number 31118)
has not been made publicly available.'


Socket AM2+ (September 2007):
http://en.wikipedia.org/wiki/Socket_AM2%2B
'"AM2r2 Processor Functional Data Sheet" (AMD document number 41607) has not
been made publicly available.'


== K8 socket <-> revision map =
http://products.amd.com/en-us/DesktopCPUResult.aspx?f1=&f2=&f3=&f4=&f5=&f6æ&f7nm+SOI&f8=&f9=&f10úlse&
Desktop:
E3 stepping -> 754, 939
E4 -> 939
E6 -> 754, 939
no F1 stepping cpus shown
F2 -> AM2
F3 -> AM2, F

Opteron:
E6 -> 939, 940
F2 -> AM2, F

Mobile:
only S1 listed, no steppings listed


http://www.cpu-world.com/Sockets/Socket%20754.html
fastest cpus for 754:
AMD Athlon 64 3700+ - ADA3700AEP5AR (ADA3700BOX), 130nm ClawHammer, core CG
AMD Mobile Athlon 64 4000+ - AMN4000BKX5BU, 90nm Newark, core E5
AMD Turion 64 Mobile technology ML-44 - TMDML44BKX5LD, 90nm E5
AMD Sempron 64 3400+ - SDA3400AIO3BX (SDA3400BXBOX), 90nm Palermo E6
AMD Mobile Sempron 3600+ - SMN3600BKX2BX, E6
"K8 Athlon XP-M" models


So we appear to have:

Table 2. K8 revision <-> vid pin count

Revision	socket		vid pin count
--------	-------		-------------
  <= E		940, 754, 939		5
  >= F		AM2, S1, F, AM2+	6


== cpuid <-> K8 revision map =
http://www.sandpile.org/ia32/cpuid.htm

cpuid_eax(1)
bits		data			notes
-----		---------------		------------------------------
27:20		extended family
19:16		extended model		see Table 3 below
13:12		cpu type	
11:8		family			always 0x0F for K8
7:4		model			
3:0		stepping		cpu-specific


Table 3. K8 extended model <-> revision

extended
model		revision
--------	--------
0000		130nm Rev C
0001		90nm Rev D
0010		90nm Rev E
0100		90nm Rev F
0101		90nm Rev F
0110		65nm Rev G
0111		65nm Rev G


excerpt from
drivers/hwmon/hwmon-vid.c
vid_which_vrm()
	u32 eax = cpuid_eax(1);
	if (eff_family = 0xF) {	/* use extended model & family */
		eff_model += ((eax & 0x000F0000)>>16)<<4;
	}

Thus for K8 where eff_family = 0x0F always, the upper 4 bits of eff_model
determine the K8 revision as per Table 3.


== K8 vid codes =
AMD 26094
Table 74, p. 283
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF
shows 5-bit vid codes; this seems to apply to sockets <= 939, revisions <= E

AMD 32559
Table 71, p. 309
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
shows 6-bit vid codes; this seems to apply to sockets >= AM2, revisions >= F
5-bit codes remain the same as in 26094


---

The above can/should probably be edited and split up, but at least some of the
references might be useful to others.


Thanks again Jean for fixing the bug so quickly.

-Frank

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Re: [lm-sensors] [PATCH 2/2] hwmon (hwmon-vid): add 6-bit vid codes

[Jean Delvare]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="windows-1252", Size: 6643 bytes --]

Hi Frank,

On Thu, 14 Aug 2008 19:59:11 -0400, Frank Myhr wrote:
> Hi Jean,
> 
> Thanks for the heads up. And even more for your patch, which I see has been
> tested and accepted. It looks good to me.
> 
> I spent a long time looking for K8 specifications (cpuid and vid pins). AMD
> doesn't make it easy--a big raspberry to them for not publishing "functional
> data sheets" for any their sockets since 939. I think it would be helpful to
> include some references to relevant cpu info in hwmon-vid (.c or doc). You
> probably have a good reference to so quickly find the 0x2F (extended) model
> cutoff for 5-vid-pin K8's.

I received the kind help of Jordan Crouse, who was able to tell me
that the split was happening with revision F CPUs. Thanks Jordan! From
there, I "simply" looked at the following 2 documents:

Revision Guide for AMD NPT Family 0Fh Processors
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf

Revision Guide for AMD Athlonâ„¢ 64 and AMD Opteronâ„¢ Processors
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf

They give the CPUID values and the revision letters for all K8 CPUs. I
came to the conclusion that extended model 0x2 or 0x3 would be the
right cutoff point. Not too sure which one to chose, as there are no
CPU listed with extended model = 0x3, as you found out yourself. So
I've chosen 0x2 as the cutoff point... But maybe 0x3 would be a better
choice, if AMD is ever going to produce a last iteration for the old
sockets.

I've mentioned these 2 reference documents in hwmon-vid.c.

> I finally arrived at the same cutoff value using a variety of references and
> combining Tables 2 and 3 below to get:
> 
> Table 1. K8 extended model <-> vid pin count
> 
> extended model	revision	vid pin count
> --------------	-------------	-------------
>    <= 0x2F	<= 90nm Rev E	5
> 0x30 - 0x3F	exist?		N/A ?
>    >= 0x40	>= 90nm Rev F	6
> 
> 
> == K8 Sockets => 
> Socket 940 (April 2003):
> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31412.pdf
> p. 35
> 5 VID pins
> http://www.cpu-world.com/Sockets/Socket%20940.html
> 
> 
> Socket 754 (September 2003):
> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31410.pdf
> p. 48
> 5 VID pins
> 
> 
> Socket 939 (June 2004):
> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31411.pdf
> p. 39
> 5 VID pins


I've read these 3 ones as well, to find out that these sockets didn't
have a 6th VID pin.

> Socket AM2 (May 2006):
> http://en.wikipedia.org/wiki/Socket_AM2
> '"AM2 Processor Functional Data Sheet" (AMD document number 31117) has not been
> made publicly available.'
> 
> 6 VID pins shown in this unofficial image
> http://www.techimo.com/forum/attachments/processors-memory-overclocking/19001d1201825486-pinout-volt-mod-socket-am2-untitled.gif
> http://www.techimo.com/forum/processors-memory-overclocking/199420-pinout-volt-mod-socket-am2.html
> 
> 
> Socket S1 (May 2006):
> http://en.wikipedia.org/wiki/Socket_S1
> '"Socket S1g1 Processor Functional Data Sheet" (AMD document number 31731) has
> not been made publicly available.'
> 
> 
> Socket F (August 2006):
> http://en.wikipedia.org/wiki/Socket_F
> '"Socket F (1207) Processor Functional Data Sheet" (AMD document number 31118)
> has not been made publicly available.'
> 
> 
> Socket AM2+ (September 2007):
> http://en.wikipedia.org/wiki/Socket_AM2%2B
> '"AM2r2 Processor Functional Data Sheet" (AMD document number 41607) has not
> been made publicly available.'
> 
> 
> == K8 socket <-> revision map => 
> http://products.amd.com/en-us/DesktopCPUResult.aspx?f1=&f2=&f3=&f4=&f5=&f6æ&f7nm+SOI&f8=&f9=&f10úlse&
> Desktop:
> E3 stepping -> 754, 939
> E4 -> 939
> E6 -> 754, 939
> no F1 stepping cpus shown
> F2 -> AM2
> F3 -> AM2, F
> 
> Opteron:
> E6 -> 939, 940
> F2 -> AM2, F
> 
> Mobile:
> only S1 listed, no steppings listed
> 
> 
> http://www.cpu-world.com/Sockets/Socket%20754.html
> fastest cpus for 754:
> AMD Athlon 64 3700+ - ADA3700AEP5AR (ADA3700BOX), 130nm ClawHammer, core CG
> AMD Mobile Athlon 64 4000+ - AMN4000BKX5BU, 90nm Newark, core E5
> AMD Turion 64 Mobile technology ML-44 - TMDML44BKX5LD, 90nm E5
> AMD Sempron 64 3400+ - SDA3400AIO3BX (SDA3400BXBOX), 90nm Palermo E6
> AMD Mobile Sempron 3600+ - SMN3600BKX2BX, E6
> "K8 Athlon XP-M" models
> 
> 
> So we appear to have:
> 
> Table 2. K8 revision <-> vid pin count
> 
> Revision	socket		vid pin count
> --------	-------		-------------
>   <= E		940, 754, 939		5
>   >= F		AM2, S1, F, AM2+	6
> 
> 
> == cpuid <-> K8 revision map => 
> http://www.sandpile.org/ia32/cpuid.htm
> 
> cpuid_eax(1)
> bits		data			notes
> -----		---------------		------------------------------
> 27:20		extended family
> 19:16		extended model		see Table 3 below
> 13:12		cpu type	
> 11:8		family			always 0x0F for K8
> 7:4		model			
> 3:0		stepping		cpu-specific
> 
> 
> Table 3. K8 extended model <-> revision
> 
> extended
> model		revision
> --------	--------
> 0000		130nm Rev C
> 0001		90nm Rev D
> 0010		90nm Rev E
> 0100		90nm Rev F
> 0101		90nm Rev F
> 0110		65nm Rev G
> 0111		65nm Rev G
> 
> 
> excerpt from
> drivers/hwmon/hwmon-vid.c
> vid_which_vrm()
> 	u32 eax = cpuid_eax(1);
> 	if (eff_family = 0xF) {	/* use extended model & family */
> 		eff_model += ((eax & 0x000F0000)>>16)<<4;
> 	}
> 
> Thus for K8 where eff_family = 0x0F always, the upper 4 bits of eff_model
> determine the K8 revision as per Table 3.
> 
> 
> == K8 vid codes => 
> AMD 26094
> Table 74, p. 283
> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF
> shows 5-bit vid codes; this seems to apply to sockets <= 939, revisions <= E

Ah, that's a good one, thanks. I've added a reference to it in
hwmon-vid.c.

> 
> AMD 32559
> Table 71, p. 309
> http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
> shows 6-bit vid codes; this seems to apply to sockets >= AM2, revisions >= F
> 5-bit codes remain the same as in 26094
> 
> 
> ---
> 
> The above can/should probably be edited and split up, but at least some of the
> references might be useful to others.

I'll post an updated patch in a moment, please confirm you're OK with
it.

> Thanks again Jean for fixing the bug so quickly.

-- 
Jean Delvare

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