* [Adeos-main] FW: [PATCH] repost: ARM FCSE @ 2008-03-07 16:19 Richard Cochran 2008-03-07 16:31 ` Gilles Chanteperdrix 2008-09-21 15:52 ` Gilles Chanteperdrix 0 siblings, 2 replies; 17+ messages in thread From: Richard Cochran @ 2008-03-07 16:19 UTC (permalink / raw) To: adeos-main [-- Attachment #1: Type: text/plain, Size: 2246 bytes --] I posted this patch today on linux-arm-kernel, but I repeat it here because there does not seem to be too much interest on that list for the ARM FCSE. I also tried to combine this patch with ipipe for kernel 2.6.20 running on the Intel IXDP465, but after booting I soon get a BUG. Anyhow, perhaps the ARM people might take a look at combining ipipe with FCSE... -----Original Message----- From: linux-arm-kernel-bounces@domain.hid [mailto:linux-arm-kernel-bounces@domain.hid] On Behalf Of Richard Cochran Sent: Friday, March 07, 2008 4:52 PM To: linux-arm-kernel@domain.hid Subject: [PATCH] repost: ARM FCSE It looks like my mailer just wrapped the line endings, and I don't know how to make it stop! (How does one escape from Outlook + Exchange?) Here is the patch once again, as an attachment. Richard --- This patch implements the ARM FCSE for Linux in a minimally intrusive way. The patch is against kernel 2.6.24, but it will also work with other recent kernels. I have tested the patch on the following machine/kernel combinations. Linksys NSLU2 2.6.21 Omicron DEVXIP 2.6.23 (this board is similar to the IXDP425) Intel IXDP465 2.6.24 Using the patch, I measured an improvement in the task switching time of about 100 us on all three platforms. The test program does something like this: 1. blocking read on network socket 2. process packet 3. send reply packet I externally measured the time from the input packet to appear on the line until the reply packet appear. I attribute the improvement in response time to the faster scheduling, due to the FCSE. KNOWN ISSUES: 1. The avoidance of flushing the D/I caches is only implemented for Xscale, in arch/arm/mm/proc-xscale.S. If you want to try other types, you should make similar changes for that type, otherwise enabling FCSE only limits your machine with no performance benefit. 2. The patch limits the total number of PIDs to 96, including each kernel and user thread. This is a bit wasteful, and it could be improved. 3. On the NSLU2, the 'ldconfig' program hangs after calling MMAP2(2) many times, but I do not know why. Looking forward to your comments, Richard [-- Attachment #2: fcse.diff --] [-- Type: application/octet-stream, Size: 11303 bytes --] diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 12161ae..088e8b9 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -651,3 +651,10 @@ config OUTER_CACHE config CACHE_L2X0 bool select OUTER_CACHE + +config ARM_FCSE + bool "Fast Context Switch Extension (EXPERIMENTAL)" + depends on EXPERIMENTAL + default n + help + Say Y here to enable the ARM FCSE. If unsure, say N. diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 846cce4..60346a9 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -17,6 +17,7 @@ #include <asm/pgtable.h> #include <asm/tlbflush.h> #include <asm/uaccess.h> +#include <asm/pid.h> #include "fault.h" @@ -439,6 +440,8 @@ do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) const struct fsr_info *inf = fsr_info + (fsr & 15) + ((fsr & (1 << 10)) >> 6); struct siginfo info; + addr = mva_to_va(addr); + if (!inf->fn(addr, fsr, regs)) return; diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index c156dda..35c4106 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -413,8 +413,10 @@ ENTRY(cpu_xscale_dcache_clean_area) */ .align 5 ENTRY(cpu_xscale_switch_mm) +#ifndef CONFIG_ARM_FCSE clean_d_cache r1, r2 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB +#endif mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 6c1c968..019a85f 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -15,6 +15,7 @@ #include <asm/glue.h> #include <asm/shmparam.h> +#include <asm/pid.h> #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) @@ -331,16 +332,19 @@ static inline void flush_cache_mm(struct mm_struct *mm) static inline void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) + if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { + start = va_to_mva(vma,start); + end = va_to_mva(vma,end); __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), vma->vm_flags); + } } static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) { if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { - unsigned long addr = user_addr & PAGE_MASK; + unsigned long addr = va_to_mva(vma,user_addr) & PAGE_MASK; __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); } } @@ -372,7 +376,7 @@ extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, * This is used for the ARM private sys_cacheflush system call. */ #define flush_cache_user_range(vma,start,end) \ - __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) + __cpuc_coherent_user_range((va_to_mva(vma,start)) & PAGE_MASK, PAGE_ALIGN(va_to_mva(vma,end))) /* * Perform necessary cache operations to ensure that data previously @@ -384,7 +388,7 @@ extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, * Perform necessary cache operations to ensure that the TLB will * see data written in the specified area. */ -#define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size) +#define clean_dcache_area(start,size) cpu_dcache_clean_area(va_to_mva_p(start), size) /* * flush_dcache_page is used when the kernel has written to the page @@ -409,7 +413,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma, extern void __flush_anon_page(struct vm_area_struct *vma, struct page *, unsigned long); if (PageAnon(page)) - __flush_anon_page(vma, page, vmaddr); + __flush_anon_page(vma, page, va_to_mva(vma,vmaddr)); } #define flush_dcache_mmap_lock(mapping) \ diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index d9bfb39..a959a3b 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h @@ -34,14 +34,23 @@ * TASK_SIZE - the maximum size of a user space task. * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area */ +#ifdef CONFIG_ARM_FCSE +#define TASK_SIZE UL(0x02000000) +#define TASK_UNMAPPED_BASE UL(0x01000000) +#else #define TASK_SIZE UL(0xbf000000) #define TASK_UNMAPPED_BASE UL(0x40000000) #endif +#endif /* * The maximum size of a 26-bit user space task. */ +#ifdef CONFIG_ARM_FCSE +#define TASK_SIZE_26 UL(0x02000000) +#else #define TASK_SIZE_26 UL(0x04000000) +#endif /* * Page offset: 3GB diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h index 53099d4..6f69eab 100644 --- a/include/asm-arm/mmu.h +++ b/include/asm-arm/mmu.h @@ -7,6 +7,9 @@ typedef struct { #ifdef CONFIG_CPU_HAS_ASID unsigned int id; #endif +#ifdef CONFIG_ARM_FCSE + unsigned int pid; +#endif unsigned int kvm_seq; } mm_context_t; diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h index 6913d02..97ed8da 100644 --- a/include/asm-arm/mmu_context.h +++ b/include/asm-arm/mmu_context.h @@ -17,6 +17,7 @@ #include <asm/cacheflush.h> #include <asm/proc-fns.h> #include <asm-generic/mm_hooks.h> +#include <asm/pid.h> void __check_kvm_seq(struct mm_struct *mm); @@ -64,7 +65,28 @@ static inline void check_context(struct mm_struct *mm) __check_kvm_seq(mm); } +#ifdef CONFIG_ARM_FCSE + +static inline int init_new_context(struct task_struct *tsk, + struct mm_struct *mm) +{ + mm->context.pid = (tsk->pid - 1) << ARMPID_SHIFT; + return 0; +} + +static void set_pid_register(struct mm_struct *mm) +{ + u32 pid = 0; + if (mm) { + pid = mm->context.pid; + } + set_armpid(pid); +} + +#else #define init_new_context(tsk,mm) 0 +#define set_pid_register(mm) do { } while(0) +#endif #endif @@ -99,6 +121,7 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) { check_context(next); + set_pid_register(next); cpu_switch_mm(next->pgd, next); if (cache_is_vivt()) cpu_clear(cpu, prev->cpu_vm_mask); diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h index 4d43945..95b4acd 100644 --- a/include/asm-arm/pgalloc.h +++ b/include/asm-arm/pgalloc.h @@ -126,6 +126,12 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep) { __pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE); +#ifdef CONFIG_ARM_FCSE + pmdp += mm->context.pid >> 20; + if (pmd_none(*pmdp)) { + __pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE); + } +#endif } #endif /* CONFIG_MMU */ diff --git a/include/asm-arm/pid.h b/include/asm-arm/pid.h new file mode 100644 index 0000000..10c9393 --- /dev/null +++ b/include/asm-arm/pid.h @@ -0,0 +1,95 @@ +/* + * Filename: include/asm-arm/pid.h + * Description: ARM Porcess ID (PID) includes for Fast Address Space Switching + * (FASS) in ARM Linux. + * Created: 14/10/2001 + * Changes: 19/02/2002 - Macros added. + * 03/08/2007 - Adapted to kernel 2.6.21 (ssm) + * Feb 2008 - Simplified a bit (rco) + * + * Copyright: (C) 2001, 2002 Adam Wiggins <awiggins@cse.unsw.edu.au> + * (C) 2007 Sebastian Smolorz <ssm@emlix.com> + * (C) 2008 Richard Cochran + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of teh GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PROC_PID_H +#define __ASM_PROC_PID_H + +#ifdef CONFIG_ARM_FCSE + +#define ARMPID_SHIFT 25 + +/* Size of PID relocation area */ +#define ARMPID_TASK_SIZE (1UL << ARMPID_SHIFT) + +/* Mask to get rid of PID from relocated address */ +#define ARMPID_MASK (ARMPID_TASK_SIZE - 1) + +/* Convert PID number ot address space location */ +#define PIDNUM_TO_PID(pid_num) ((pid_num) << ARMPID_SHIFT) + +/* And back again */ +#define PID_TO_PIDNUM(pid) ((pid) >> ARMPID_SHIFT) + +/* Gets the ARM PID register value from a Modified Virtual Address (MVA) */ +#define MVA_TO_PID(mva) ((mva) & ~ARMPID_MASK) +#define MVA_TO_PIDNUM(mva) (PID_TO_PIDNUM(MVA_TO_PID(mva))) +#define MVA_TO_VA(mva) (mva & ARMPID_MASK) +#define VA_TO_MVA(va) (va | get_armpid()) + +/* Find out the CPD index offset due to ARM PID relocation */ +#define ARMPID_CPD_OFFSET(pid) ((pid) >> PGDIR_SHIFT) + +/* Sets the CPU's PID Register */ +static inline void set_armpid(u32 pid) +{ + __asm__ __volatile__("mcr p15, 0, %0, c13, c0, 0" + : : "r" (pid)); +} + +/* Returns the state of the CPU's PID Register */ +static inline u32 get_armpid(void) +{ + u32 pid; + __asm__ __volatile__("mrc p15, 0, %0, c13, c0, 0 @ Get ARM PID" + : "=&r" (pid) : ); + return (pid & (~ARMPID_MASK)); +} + +static inline unsigned long mva_to_va(unsigned long mva) +{ + unsigned long pid = get_armpid(); + if (pid && (pid == MVA_TO_PID(mva))) { + return MVA_TO_VA(mva); + } + return mva; +} + +static inline unsigned long va_to_mva(struct vm_area_struct *vma, + unsigned long va) +{ + if (va < ARMPID_TASK_SIZE) { + return VA_TO_MVA(va); + } + return va; +} + +static inline void* va_to_mva_p(void *va) +{ + u32 tmp = (u32) va; + if (tmp < ARMPID_TASK_SIZE) { + va = (void*) VA_TO_MVA(tmp); + } + return va; +} + +#else /* CONFIG_ARM_FCSE */ +#define mva_to_va(x) (x) +#define va_to_mva(vma,x) (x) +#define va_to_mva_p(x) (x) +#endif + +#endif diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h index 71be4fd..81d963d 100644 --- a/include/asm-arm/tlbflush.h +++ b/include/asm-arm/tlbflush.h @@ -158,6 +158,7 @@ #ifndef __ASSEMBLY__ #include <linux/sched.h> +#include <asm/pid.h> struct cpu_tlb_fns { void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *); @@ -325,7 +326,7 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) const int zero = 0; const unsigned int __tlb_flag = __cpu_tlb_flags; - uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); + uaddr = (va_to_mva(vma,uaddr) & PAGE_MASK) | ASID(vma->vm_mm); if (tlb_flag(TLB_WB)) dsb(); diff --git a/include/linux/threads.h b/include/linux/threads.h index 38d1a5d..ed0d5a2 100644 --- a/include/linux/threads.h +++ b/include/linux/threads.h @@ -24,13 +24,21 @@ /* * This controls the default maximum pid allocated to a process */ +#ifdef CONFIG_ARM_FCSE +#define PID_MAX_DEFAULT 96 +#else #define PID_MAX_DEFAULT (CONFIG_BASE_SMALL ? 0x1000 : 0x8000) +#endif /* * A maximum of 4 million PIDs should be enough for a while. * [NOTE: PID/TIDs are limited to 2^29 ~= 500+ million, see futex.h.] */ +#ifdef CONFIG_ARM_FCSE +#define PID_MAX_LIMIT 96 +#else #define PID_MAX_LIMIT (CONFIG_BASE_SMALL ? PAGE_SIZE * 8 : \ (sizeof(long) > 4 ? 4 * 1024 * 1024 : PID_MAX_DEFAULT)) +#endif #endif diff --git a/kernel/pid.c b/kernel/pid.c index c6e3f9f..11c505e 100644 --- a/kernel/pid.c +++ b/kernel/pid.c @@ -37,7 +37,11 @@ struct pid init_struct_pid = INIT_STRUCT_PID; int pid_max = PID_MAX_DEFAULT; +#ifdef CONFIG_ARM_FCSE +#define RESERVED_PIDS 20 +#else #define RESERVED_PIDS 300 +#endif int pid_max_min = RESERVED_PIDS + 1; int pid_max_max = PID_MAX_LIMIT; [-- Attachment #3: ATT18375870.txt --] [-- Type: text/plain, Size: 274 bytes --] ------------------------------------------------------------------- List admin: http://lists.arm.linux.org.uk/mailman/listinfo/linux-arm-kernel FAQ: http://www.arm.linux.org.uk/mailinglists/faq.php Etiquette: http://www.arm.linux.org.uk/mailinglists/etiquette.php ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-03-07 16:19 [Adeos-main] FW: [PATCH] repost: ARM FCSE Richard Cochran @ 2008-03-07 16:31 ` Gilles Chanteperdrix 2008-09-21 15:52 ` Gilles Chanteperdrix 1 sibling, 0 replies; 17+ messages in thread From: Gilles Chanteperdrix @ 2008-03-07 16:31 UTC (permalink / raw) To: Richard Cochran; +Cc: adeos-main On Fri, Mar 7, 2008 at 5:19 PM, Richard Cochran <richard.cochran@domain.hid> wrote: > I posted this patch today on linux-arm-kernel, but I repeat it > here because there does not seem to be too much interest on that > list for the ARM FCSE. > > I also tried to combine this patch with ipipe for kernel 2.6.20 > running on the Intel IXDP465, but after booting I soon get a BUG. Do you get a bug with I-pipe alone ? Or with Xenomai ? If with Xenomai, you should probably change Xenomai context switch routine to match Linux context switch routine (adding a call to set_pid, if I understood your patch correctly). > > Anyhow, perhaps the ARM people might take a look at combining > ipipe with FCSE... I hope that others can test it: the machine with which I work at home is an AT91RM9200, without FCSE support, and the IXP465 I have at work runs more than 96 pids. There is something I did not understand in your patch: do you reserve PIDs for shared libraries ? How do you handle threads stacks ? The old FASS patch had problems with this. Also, it is completely unrelated, did you see the recent post about write buffer coalescence on the Linux arm kernel mailing list ? From my test on IXP465 it seems that these machines are affected as well. -- Gilles Chanteperdrix ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-03-07 16:19 [Adeos-main] FW: [PATCH] repost: ARM FCSE Richard Cochran 2008-03-07 16:31 ` Gilles Chanteperdrix @ 2008-09-21 15:52 ` Gilles Chanteperdrix 2008-09-21 16:30 ` Gilles Chanteperdrix 2008-09-23 18:32 ` Gilles Chanteperdrix 1 sibling, 2 replies; 17+ messages in thread From: Gilles Chanteperdrix @ 2008-09-21 15:52 UTC (permalink / raw) To: Richard Cochran; +Cc: adeos-main Richard Cochran wrote: > I posted this patch today on linux-arm-kernel, but I repeat it > here because there does not seem to be too much interest on that > list for the ARM FCSE. > > I also tried to combine this patch with ipipe for kernel 2.6.20 > running on the Intel IXDP465, but after booting I soon get a BUG. > > Anyhow, perhaps the ARM people might take a look at combining > ipipe with FCSE... Ok. Six monthes later, I finally gave a try to your patch on at91rm9200, which supports FCSE as well. When booting, I get random segmentation faults (either with or without the I-pipe), assertion which fails in glibc, and such things. I looked at the code, and have a few questions: - in cpu_switch_mm, you comment out the cache flush but keep the TLB flush, is the TLB flush really needed ? - in pmd_populate (file include/asm-arm/pgalloc.h), you populate two pmds, does not this look wrong ? I mean it looks like pmd_populate is called with the two "kinds" (translated and untranslated) addresses, which should not happen. - in exit_mmap (file mm/mmap.c), we should arrange for flush_cache_mm to flush the whole cache (I mean without consulting mm->cpu_vm_mask) to avoid keeping stale entries pointing to pages which are going to be returned to the system. I tried to change this, but I still get the random failures. - anyone still has the old FASS patch ? Perhaps by looking at it we could find what is missing in your patch. -- Gilles. ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-09-21 15:52 ` Gilles Chanteperdrix @ 2008-09-21 16:30 ` Gilles Chanteperdrix 2008-09-23 18:32 ` Gilles Chanteperdrix 1 sibling, 0 replies; 17+ messages in thread From: Gilles Chanteperdrix @ 2008-09-21 16:30 UTC (permalink / raw) To: Richard Cochran; +Cc: adeos-main Gilles Chanteperdrix wrote: > - anyone still has the old FASS patch ? Perhaps by looking at it we > could find what is missing in your patch. Ok. Found it: http://www.ertos.nicta.com.au/software/fass/ But this looks way more complicated... -- Gilles. ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-09-21 15:52 ` Gilles Chanteperdrix 2008-09-21 16:30 ` Gilles Chanteperdrix @ 2008-09-23 18:32 ` Gilles Chanteperdrix 2008-09-24 5:47 ` Richard Cochran 2008-09-27 17:53 ` Gilles Chanteperdrix 1 sibling, 2 replies; 17+ messages in thread From: Gilles Chanteperdrix @ 2008-09-23 18:32 UTC (permalink / raw) To: Richard Cochran; +Cc: adeos-main Gilles Chanteperdrix wrote: > Richard Cochran wrote: >> I posted this patch today on linux-arm-kernel, but I repeat it >> here because there does not seem to be too much interest on that >> list for the ARM FCSE. >> >> I also tried to combine this patch with ipipe for kernel 2.6.20 >> running on the Intel IXDP465, but after booting I soon get a BUG. >> >> Anyhow, perhaps the ARM people might take a look at combining >> ipipe with FCSE... > > Ok. Six monthes later, I finally gave a try to your patch on at91rm9200, > which supports FCSE as well. > > When booting, I get random segmentation faults (either with or without > the I-pipe), assertion which fails in glibc, and such things. A small update: I get the same random failures with a vanilla kernel (without I-pipe patch at all). I will now investigate pmd_populate. -- Gilles. ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-09-23 18:32 ` Gilles Chanteperdrix @ 2008-09-24 5:47 ` Richard Cochran 2008-09-24 7:38 ` Gilles Chanteperdrix 2008-09-27 17:53 ` Gilles Chanteperdrix 1 sibling, 1 reply; 17+ messages in thread From: Richard Cochran @ 2008-09-24 5:47 UTC (permalink / raw) To: Gilles Chanteperdrix; +Cc: adeos-main > -----Original Message----- From: Gilles Chanteperdrix > A small update: I get the same random failures with a vanilla kernel > (without I-pipe patch at all). Can you tell me: gcc/binutils/glibc versions, and kernel .config ? Thanks, Richard ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-09-24 5:47 ` Richard Cochran @ 2008-09-24 7:38 ` Gilles Chanteperdrix 0 siblings, 0 replies; 17+ messages in thread From: Gilles Chanteperdrix @ 2008-09-24 7:38 UTC (permalink / raw) To: Richard Cochran; +Cc: adeos-main [-- Attachment #1: Type: text/plain, Size: 872 bytes --] Richard Cochran wrote: >> -----Original Message----- From: Gilles Chanteperdrix >> A small update: I get the same random failures with a vanilla kernel >> (without I-pipe patch at all). > > Can you tell me: gcc/binutils/glibc versions, and kernel .config ? I use the toolchain from CodeSourcery version 2007q3, glibc is copied from the toolchain and is 2.5, gcc is 4.2.1, binutils is 2.16. Kernel config attached. Note that to get the issue, I have to launch a dd if=/dev/zero of=/dev/null, which starts flawlessly most of the time, then run a loop of ls -lR, which starts flawlessly as well. Then run the "run" script of Xenomai latency test, and there I have bugs. I really think the double mapping is a problem, who knows what mapping the processor choose if it has the choice ? It may not even choose the same mapping on xscale and ar920t... -- Gilles. [-- Attachment #2: vanilla-config --] [-- Type: text/plain, Size: 29616 bytes --] # # Automatically generated make config: don't edit # Linux kernel version: 2.6.26 # Tue Sep 23 19:45:29 2008 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_MMU=y # CONFIG_NO_IOPORT is not set CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_SUPPORTS_AOUT=y CONFIG_ZONE_DMA=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # # General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y # CONFIG_SWAP is not set CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CGROUPS is not set CONFIG_GROUP_SCHED=y CONFIG_FAIR_GROUP_SCHED=y # CONFIG_RT_GROUP_SCHED is not set CONFIG_USER_SCHED=y # CONFIG_CGROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set # CONFIG_IPC_NS is not set # CONFIG_USER_NS is not set # CONFIG_PID_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set # CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y # CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y # CONFIG_HAVE_DMA_ATTRS is not set CONFIG_PROC_PAGE_MONITOR=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set # CONFIG_BLK_DEV_BSG is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" CONFIG_CLASSIC_RCU=y # # System Type # # CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set CONFIG_ARCH_AT91=y # CONFIG_ARCH_CLPS7500 is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_CO285 is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set # CONFIG_ARCH_IMX is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set # CONFIG_ARCH_IXP23XX is not set # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set # CONFIG_ARCH_KS8695 is not set # CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_MXC is not set # CONFIG_ARCH_ORION5X is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set # CONFIG_ARCH_MSM7X00A is not set # # Boot options # # # Power management # # # Atmel AT91 System-on-Chip # CONFIG_ARCH_AT91RM9200=y # CONFIG_ARCH_AT91SAM9260 is not set # CONFIG_ARCH_AT91SAM9261 is not set # CONFIG_ARCH_AT91SAM9263 is not set # CONFIG_ARCH_AT91SAM9RL is not set # CONFIG_ARCH_AT91CAP9 is not set # CONFIG_ARCH_AT91X40 is not set CONFIG_AT91_PMC_UNIT=y # # AT91RM9200 Board Type # # CONFIG_MACH_ONEARM is not set # CONFIG_ARCH_AT91RM9200DK is not set # CONFIG_MACH_AT91RM9200EK is not set # CONFIG_MACH_CSB337 is not set CONFIG_MACH_CSB637=y # CONFIG_MACH_CARMEVA is not set # CONFIG_MACH_ATEB9200 is not set # CONFIG_MACH_KB9200 is not set # CONFIG_MACH_PICOTUX2XX is not set # CONFIG_MACH_KAFA is not set # CONFIG_MACH_ECBAT91 is not set # # AT91 Board Options # # # AT91 Feature Selections # CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_TIMER_HZ=128 CONFIG_AT91_EARLY_DBGU=y # CONFIG_AT91_EARLY_USART0 is not set # CONFIG_AT91_EARLY_USART1 is not set # CONFIG_AT91_EARLY_USART2 is not set # CONFIG_AT91_EARLY_USART3 is not set # CONFIG_AT91_EARLY_USART4 is not set # CONFIG_AT91_EARLY_USART5 is not set # # Processor Type # CONFIG_CPU_32=y CONFIG_CPU_ARM920T=y CONFIG_CPU_32v4T=y CONFIG_CPU_ABRT_EV4T=y CONFIG_CPU_PABRT_NOIFAR=y CONFIG_CPU_CACHE_V4WT=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_COPY_V4WB=y CONFIG_CPU_TLB_V4WBI=y CONFIG_CPU_CP15=y CONFIG_CPU_CP15_MMU=y # # Processor Features # # CONFIG_ARM_THUMB is not set # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_DCACHE_WRITETHROUGH is not set # CONFIG_OUTER_CACHE is not set CONFIG_ARM_FCSE=y # # Bus support # # CONFIG_PCI_SYSCALL is not set # CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_PCCARD=y # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=y CONFIG_PCMCIA_LOAD_CIS=y CONFIG_PCMCIA_IOCTL=y # # PC-card bridges # CONFIG_AT91_CF=y # # Kernel Features # CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_PREEMPT=y CONFIG_HZ=128 CONFIG_AEABI=y CONFIG_OABI_COMPAT=y # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4096 # CONFIG_RESOURCES_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y CONFIG_LEDS=y CONFIG_LEDS_CPU=y CONFIG_ALIGNMENT_TRAP=y # # Boot options # CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw" # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set # # Floating point emulation # # # At least one emulation must be selected # CONFIG_FPE_NWFPE=y # CONFIG_FPE_NWFPE_XP is not set # CONFIG_FPE_FASTFPE is not set # # Userspace binary formats # CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_AOUT is not set # CONFIG_BINFMT_MISC is not set # # Power management options # # CONFIG_PM is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y # # Networking # CONFIG_NET=y # # Networking options # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y # CONFIG_IP_MULTICAST is not set # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_ARPD is not set # CONFIG_SYN_COOKIES is not set # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y # CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_NET_SCHED is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set # # Wireless # # CONFIG_CFG80211 is not set # CONFIG_WIRELESS_EXT is not set # CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set # # Device Drivers # # # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_AFS_PARTS is not set # CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers # CONFIG_MTD_CHAR=y CONFIG_MTD_BLKDEVS=y CONFIG_MTD_BLOCK=y # CONFIG_FTL is not set # CONFIG_NFTL is not set # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set # CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=y # CONFIG_MTD_JEDECPROBE is not set CONFIG_MTD_GEN_PROBE=y # CONFIG_MTD_CFI_ADV_OPTIONS is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y # CONFIG_MTD_CFI_I4 is not set # CONFIG_MTD_CFI_I8 is not set CONFIG_MTD_CFI_INTELEXT=y # CONFIG_MTD_CFI_AMDSTD is not set # CONFIG_MTD_CFI_STAA is not set CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set CONFIG_MTD_PHYSMAP=y CONFIG_MTD_PHYSMAP_START=0x0 CONFIG_MTD_PHYSMAP_LEN=0x0 CONFIG_MTD_PHYSMAP_BANKWIDTH=0 # CONFIG_MTD_ARM_INTEGRATOR is not set # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set # CONFIG_MTD_BLOCK2MTD is not set # # Disk-On-Chip Device Drivers # # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set # CONFIG_MTD_NAND is not set # CONFIG_MTD_ONENAND is not set # # UBI - Unsorted block images # # CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set CONFIG_MISC_DEVICES=y # CONFIG_ATMEL_PWM is not set CONFIG_ATMEL_TCLIB=y CONFIG_ATMEL_TCB_CLKSRC=y CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0 # CONFIG_EEPROM_93CX6 is not set # CONFIG_ATMEL_SSC is not set # CONFIG_ENCLOSURE_SERVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # # CONFIG_BLK_DEV_SD is not set # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set # CONFIG_ATA is not set # CONFIG_MD is not set CONFIG_NETDEVICES=y # CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set # CONFIG_PHYLIB is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y CONFIG_ARM_AT91_ETHER=y # CONFIG_AX88796 is not set # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set # CONFIG_B44 is not set CONFIG_NETDEV_1000=y # CONFIG_E1000E_ENABLED is not set CONFIG_NETDEV_10000=y # # Wireless LAN # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set # CONFIG_IWLWIFI_LEDS is not set # # USB Network Adapters # # CONFIG_USB_CATC is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set # CONFIG_NET_PCMCIA is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_ISDN is not set # # Input device support # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set # # Hardware I/O ports # # CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set # # Character devices # CONFIG_VT=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # # Serial drivers # # CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # CONFIG_SERIAL_ATMEL=y CONFIG_SERIAL_ATMEL_CONSOLE=y CONFIG_SERIAL_ATMEL_PDC=y # CONFIG_SERIAL_ATMEL_TTYAT is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=m # CONFIG_NVRAM is not set # CONFIG_R3964 is not set # # PCMCIA character devices # # CONFIG_SYNCLINK_CS is not set # CONFIG_CARDMAN_4000 is not set # CONFIG_CARDMAN_4040 is not set # CONFIG_IPWIRELESS is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_CHARDEV=y # # I2C Hardware Bus support # # CONFIG_I2C_GPIO is not set # CONFIG_I2C_OCORES is not set # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_STUB is not set # CONFIG_I2C_TINY_USB is not set # CONFIG_I2C_PCA_PLATFORM is not set # # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set # CONFIG_SENSORS_LM80 is not set # CONFIG_SENSORS_LM83 is not set # CONFIG_SENSORS_LM85 is not set # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set CONFIG_WATCHDOG=y CONFIG_WATCHDOG_NOWAYOUT=y # # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set CONFIG_AT91RM9200_WATCHDOG=y # # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set # # Sonics Silicon Backplane # CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # # CONFIG_MFD_SM501 is not set # CONFIG_MFD_ASIC3 is not set # CONFIG_HTC_PASIC3 is not set # # Multimedia devices # # # Multimedia core support # # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set # CONFIG_VIDEO_MEDIA is not set # # Multimedia drivers # # CONFIG_DAB is not set # # Graphics support # # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support # # CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y # # Sound # # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y CONFIG_HID_DEBUG=y # CONFIG_HIDRAW is not set # # USB Input Devices # # CONFIG_USB_HID is not set # # USB HID Boot Protocol drivers # # CONFIG_USB_KBD is not set # CONFIG_USB_MOUSE is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y # CONFIG_USB_ARCH_HAS_EHCI is not set CONFIG_USB=y CONFIG_USB_DEBUG=y # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # CONFIG_USB_DEVICEFS=y CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set # # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # # # may also be needed; see USB_STORAGE Help for more information # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set # CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # # USB Imaging devices # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set CONFIG_USB_MON=y # # USB port drivers # CONFIG_USB_SERIAL=y CONFIG_USB_SERIAL_CONSOLE=y CONFIG_USB_EZUSB=y CONFIG_USB_SERIAL_GENERIC=y # CONFIG_USB_SERIAL_AIRCABLE is not set # CONFIG_USB_SERIAL_AIRPRIME is not set # CONFIG_USB_SERIAL_ARK3116 is not set # CONFIG_USB_SERIAL_BELKIN is not set # CONFIG_USB_SERIAL_CH341 is not set # CONFIG_USB_SERIAL_WHITEHEAT is not set # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set # CONFIG_USB_SERIAL_CP2101 is not set # CONFIG_USB_SERIAL_CYPRESS_M8 is not set # CONFIG_USB_SERIAL_EMPEG is not set CONFIG_USB_SERIAL_FTDI_SIO=y # CONFIG_USB_SERIAL_FUNSOFT is not set # CONFIG_USB_SERIAL_VISOR is not set # CONFIG_USB_SERIAL_IPAQ is not set # CONFIG_USB_SERIAL_IR is not set # CONFIG_USB_SERIAL_EDGEPORT is not set # CONFIG_USB_SERIAL_EDGEPORT_TI is not set # CONFIG_USB_SERIAL_GARMIN is not set # CONFIG_USB_SERIAL_IPW is not set # CONFIG_USB_SERIAL_IUU is not set # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set CONFIG_USB_SERIAL_KEYSPAN=y CONFIG_USB_SERIAL_KEYSPAN_MPR=y CONFIG_USB_SERIAL_KEYSPAN_USA28=y CONFIG_USB_SERIAL_KEYSPAN_USA28X=y CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y CONFIG_USB_SERIAL_KEYSPAN_USA19=y CONFIG_USB_SERIAL_KEYSPAN_USA18X=y CONFIG_USB_SERIAL_KEYSPAN_USA19W=y CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y CONFIG_USB_SERIAL_KEYSPAN_USA49W=y CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y # CONFIG_USB_SERIAL_KLSI is not set # CONFIG_USB_SERIAL_KOBIL_SCT is not set CONFIG_USB_SERIAL_MCT_U232=y # CONFIG_USB_SERIAL_MOS7720 is not set # CONFIG_USB_SERIAL_MOS7840 is not set # CONFIG_USB_SERIAL_MOTOROLA is not set # CONFIG_USB_SERIAL_NAVMAN is not set # CONFIG_USB_SERIAL_PL2303 is not set # CONFIG_USB_SERIAL_OTI6858 is not set # CONFIG_USB_SERIAL_SPCP8X5 is not set # CONFIG_USB_SERIAL_HP4X is not set # CONFIG_USB_SERIAL_SAFE is not set # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set # CONFIG_USB_SERIAL_TI is not set # CONFIG_USB_SERIAL_CYBERJACK is not set # CONFIG_USB_SERIAL_XIRCOM is not set # CONFIG_USB_SERIAL_OPTION is not set # CONFIG_USB_SERIAL_OMNINET is not set # CONFIG_USB_SERIAL_DEBUG is not set # # USB Miscellaneous drivers # # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_AUERSWALD is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set # CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set # CONFIG_NEW_LEDS is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set # CONFIG_UIO is not set # # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set # CONFIG_EXT3_FS is not set # CONFIG_EXT4DEV_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set # # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # # CONFIG_MSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # # Pseudo filesystems # CONFIG_PROC_FS=y CONFIG_PROC_SYSCTL=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set # # Miscellaneous filesystems # # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=y # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y # CONFIG_NFSD is not set CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y # CONFIG_SUNRPC_BIND34 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y # CONFIG_NLS is not set # CONFIG_DLM is not set # # Kernel hacking # # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set CONFIG_DEBUG_PREEMPT=y # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_LOCK_ALLOC=y # CONFIG_PROVE_LOCKING is not set CONFIG_LOCKDEP=y # CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_LOCKDEP is not set CONFIG_DEBUG_SPINLOCK_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set CONFIG_STACKTRACE=y # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set CONFIG_DEBUG_VM=y # CONFIG_DEBUG_WRITECOUNT is not set CONFIG_DEBUG_LIST=y # CONFIG_DEBUG_SG is not set CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_SAMPLES is not set CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y # CONFIG_DEBUG_ICEDCC is not set # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y # # Crypto core or helper # CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_TEST is not set # # Authenticated Encryption with Associated Data # # CONFIG_CRYPTO_CCM is not set # CONFIG_CRYPTO_GCM is not set # CONFIG_CRYPTO_SEQIV is not set # # Block modes # CONFIG_CRYPTO_CBC=y # CONFIG_CRYPTO_CTR is not set # CONFIG_CRYPTO_CTS is not set # CONFIG_CRYPTO_ECB is not set # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # # Hash modes # # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # # Ciphers # # CONFIG_CRYPTO_AES is not set # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # # Compression # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set CONFIG_CRYPTO_HW=y # # Library routines # CONFIG_BITREVERSE=y # CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_GENERIC_FIND_NEXT_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-09-23 18:32 ` Gilles Chanteperdrix 2008-09-24 5:47 ` Richard Cochran @ 2008-09-27 17:53 ` Gilles Chanteperdrix 2008-10-02 8:44 ` Gilles Chanteperdrix 1 sibling, 1 reply; 17+ messages in thread From: Gilles Chanteperdrix @ 2008-09-27 17:53 UTC (permalink / raw) To: Richard Cochran; +Cc: adeos-main Gilles Chanteperdrix wrote: > Gilles Chanteperdrix wrote: >> Richard Cochran wrote: >>> I posted this patch today on linux-arm-kernel, but I repeat it >>> here because there does not seem to be too much interest on that >>> list for the ARM FCSE. >>> >>> I also tried to combine this patch with ipipe for kernel 2.6.20 >>> running on the Intel IXDP465, but after booting I soon get a BUG. >>> >>> Anyhow, perhaps the ARM people might take a look at combining >>> ipipe with FCSE... >> Ok. Six monthes later, I finally gave a try to your patch on at91rm9200, >> which supports FCSE as well. >> >> When booting, I get random segmentation faults (either with or without >> the I-pipe), assertion which fails in glibc, and such things. > > A small update: I get the same random failures with a vanilla kernel > (without I-pipe patch at all). > > I will now investigate pmd_populate. Hi Richard, I changed a few bits here and there in your patch, but I believe the biggest problem was that Linux seem to recycle pids faster than it recycles mm_struct, so we ended up with processes sharing the same space, and since the pid allocation mechanism was a bit too naive for multi-threaded applications, I changed it to a bitfield based solution. I now have an FCSE kernel which seems much more stable (and without the double mapping either). This is the good news. The bad news is that I still get mysterious crashes. So, will now investigate. Regards. -- Gilles. ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-09-27 17:53 ` Gilles Chanteperdrix @ 2008-10-02 8:44 ` Gilles Chanteperdrix 2008-10-02 14:54 ` Richard Cochran 2008-10-02 22:04 ` Bosko Radivojevic 0 siblings, 2 replies; 17+ messages in thread From: Gilles Chanteperdrix @ 2008-10-02 8:44 UTC (permalink / raw) To: Richard Cochran; +Cc: adeos-main [-- Attachment #1: Type: text/plain, Size: 2065 bytes --] Gilles Chanteperdrix wrote: > Gilles Chanteperdrix wrote: >> Gilles Chanteperdrix wrote: >>> Richard Cochran wrote: >>>> I posted this patch today on linux-arm-kernel, but I repeat it >>>> here because there does not seem to be too much interest on that >>>> list for the ARM FCSE. >>>> >>>> I also tried to combine this patch with ipipe for kernel 2.6.20 >>>> running on the Intel IXDP465, but after booting I soon get a BUG. >>>> >>>> Anyhow, perhaps the ARM people might take a look at combining >>>> ipipe with FCSE... >>> Ok. Six monthes later, I finally gave a try to your patch on at91rm9200, >>> which supports FCSE as well. >>> >>> When booting, I get random segmentation faults (either with or without >>> the I-pipe), assertion which fails in glibc, and such things. >> A small update: I get the same random failures with a vanilla kernel >> (without I-pipe patch at all). >> >> I will now investigate pmd_populate. > > Hi Richard, > > I changed a few bits here and there in your patch, but I believe the > biggest problem was that Linux seem to recycle pids faster than it > recycles mm_struct, so we ended up with processes sharing the same > space, and since the pid allocation mechanism was a bit too naive for > multi-threaded applications, I changed it to a bitfield based solution. > I now have an FCSE kernel which seems much more stable (and without the > double mapping either). This is the good news. > > The bad news is that I still get mysterious crashes. So, will now > investigate. Hi, found the reason for the crash. The system seems to run stable now. Here comes the patch. Could you test it and confirm that there is no problem for you ? Bosko: could you test it for arm926 ? I made the needed change in arch/arm/mm/proc-arm926.S, but did not check it yet. The patch is for vanilla Linux, I did not retest it with Xenomai yet (though I tested the previous version with the random crashes, and observed a 200us user-space latency instead of the usual 300us). Regards. -- Gilles. [-- Attachment #2: fcse.2.diff --] [-- Type: text/plain, Size: 23923 bytes --] diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index ad455ff..4481a30 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -10,6 +10,7 @@ obj-y := compat.o entry-armv.o entry-common.o irq.o \ process.o ptrace.o setup.o signal.o \ sys_arm.o stacktrace.o time.o traps.o +obj-$(CONFIG_ARM_FCSE) += fcse.o obj-$(CONFIG_ISA_DMA_API) += dma.o obj-$(CONFIG_ARCH_ACORN) += ecard.o obj-$(CONFIG_FIQ) += fiq.o diff --git a/arch/arm/kernel/fcse.c b/arch/arm/kernel/fcse.c new file mode 100644 index 0000000..1900a79 --- /dev/null +++ b/arch/arm/kernel/fcse.c @@ -0,0 +1,37 @@ +#include <linux/bitops.h> +#include <linux/memory.h> +#include <linux/spinlock.h> +#include <linux/bitops.h> +#include <asm/fcse.h> + +#define MAX_PID (MODULE_START / FCSE_PID_TASK_SIZE) +#define PIDS_LONGS (MAX_PID + 8 * sizeof(long) - 1) / (8 * sizeof(long)) + +static spinlock_t fcse_lock = SPIN_LOCK_UNLOCKED; +static unsigned long fcse_pids_bits[PIDS_LONGS]; + +int fcse_pid_alloc(void) +{ + unsigned long flags; + unsigned bit; + + spin_lock_irqsave(&fcse_lock, flags); + bit = find_first_zero_bit(fcse_pids_bits, MAX_PID); + if (bit == MAX_PID) { + spin_unlock(&fcse_lock); + return -1; + } + set_bit(bit, fcse_pids_bits); + spin_unlock_irqrestore(&fcse_lock, flags); + + return bit; +} + +void fcse_pid_free(unsigned pid) +{ + unsigned long flags; + + spin_lock_irqsave(&fcse_lock, flags); + pid = test_and_clear_bit(pid, fcse_pids_bits); + spin_unlock_irqrestore(&fcse_lock, flags); +} diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index eefae1d..b13d8a5 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -32,6 +32,7 @@ #include <asm/processor.h> #include <asm/tlbflush.h> #include <asm/ptrace.h> +#include <asm/fcse.h> /* * bitmask of present and online CPUs. @@ -736,14 +737,14 @@ void flush_tlb_all(void) void flush_tlb_mm(struct mm_struct *mm) { - cpumask_t mask = mm->cpu_vm_mask; + cpumask_t mask = fcse_tlb_mask(mm); on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, 1, mask); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) { - cpumask_t mask = vma->vm_mm->cpu_vm_mask; + cpumask_t mask = fcse_tlb_mask(vma->vm_mm); struct tlb_args ta; ta.ta_vma = vma; @@ -764,7 +765,7 @@ void flush_tlb_kernel_page(unsigned long kaddr) void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - cpumask_t mask = vma->vm_mm->cpu_vm_mask; + cpumask_t mask = fcse_tlb_mask(vma->vm_mm); struct tlb_args ta; ta.ta_vma = vma; diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index 0128687..732f442 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -61,7 +61,18 @@ inline long do_mmap2( if (file) fput(file); +#ifdef CONFIG_ARM_FCSE + /* FIXME, this really sucks, and we should really recheck in mremap and + munmap */ + if (likely((unsigned) error < (unsigned)(-4096)) + && (flags & MAP_SHARED) && (prot & PROT_WRITE)) { + struct vm_area_struct *vma = find_vma(current->mm, error); + if (vma->vm_page_prot & (L_PTE_CACHEABLE | L_PTE_BUFFERABLE)) + ++current->mm->context.mappings_needing_flush; + } +#endif out: + return error; } diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 5595fdd..466e230 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -35,7 +35,7 @@ static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" }; #ifdef CONFIG_DEBUG_USER -unsigned int user_debug; +unsigned int user_debug = 0; static int __init user_debug_setup(char *str) { diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 33ed048..6c40ac0 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -716,3 +716,10 @@ config CACHE_L2X0 select OUTER_CACHE help This option enables the L2x0 PrimeCell. + +config ARM_FCSE + bool "Fast Context Switch Extension (EXPERIMENTAL)" + depends on EXPERIMENTAL + default n + help + Say Y here to enable the ARM FCSE. If unsure, say N. diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 28ad7ab..2235ab8 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -13,11 +13,13 @@ #include <linux/mm.h> #include <linux/init.h> #include <linux/kprobes.h> +#include <linux/kallsyms.h> #include <asm/system.h> #include <asm/pgtable.h> #include <asm/tlbflush.h> #include <asm/uaccess.h> +#include <asm/fcse.h> #include "fault.h" @@ -44,6 +46,65 @@ static inline int notify_page_fault(struct pt_regs *regs, unsigned int fsr) } #endif +#ifdef CONFIG_ARM_FCSE +void check_pgd(struct mm_struct *mm) +{ + pgd_t *pgd = mm->pgd; + unsigned i, start = 0, end = 0; + + for (i = 0; i < (mm->context.pid >> PGDIR_SHIFT); i++) + if (((unsigned long *)(pgd + i))[0] + || ((unsigned long *)(pgd + i))[1]) { + if (!start) + start = i; + end = i + 1; + } else { + if (start) { + printk("\nError pgd not null at 0x%08x - 0x%08x," + " pid: 0x%08lx\n", + start << PGDIR_SHIFT, + end << PGDIR_SHIFT, + mm->context.pid); + start = 0; + } + } + + if (start) { + printk("\nError pgd not null at 0x%08x - 0x%08x," + " pid: 0x%08lx\n", + start << PGDIR_SHIFT, + end << PGDIR_SHIFT, + mm->context.pid); + start = 0; + } + for (i = ((mm->context.pid + 0x2000000) >> PGDIR_SHIFT); + i < (MODULE_START >> PGDIR_SHIFT); i++) + if (((unsigned long *)(pgd + i))[0] + || ((unsigned long *)(pgd + i))[1]) { + if (!start) + start = i; + end = i + 1; + } else { + if (start) { + printk("\nError pgd not null at 0x%08x - 0x%08x," + " pid: 0x%08lx\n", + start << PGDIR_SHIFT, + end << PGDIR_SHIFT, + mm->context.pid); + start = 0; + } + } + if (start) { + printk("\nError pgd not null at 0x%08x - 0x%08x," + " pid: 0x%08lx\n", + start << PGDIR_SHIFT, + end << PGDIR_SHIFT, + mm->context.pid); + start = 0; + } +} +#endif /* CONFIG_ARM_FCSE */ + /* * This is useful to dump out the page tables associated with * 'addr' in mm 'mm'. @@ -55,6 +116,10 @@ void show_pte(struct mm_struct *mm, unsigned long addr) if (!mm) mm = &init_mm; +#ifdef CONFIG_ARM_FCSE + printk(KERN_ALERT "fcse pid: %ld, 0x%08lx\n", + mm->context.pid >> FCSE_PID_SHIFT, mm->context.pid); +#endif /* CONFIG_ARM_FCSE */ printk(KERN_ALERT "pgd = %p\n", mm->pgd); pgd = pgd_offset(mm, addr); printk(KERN_ALERT "[%08lx] *pgd=%08lx", addr, pgd_val(*pgd)); @@ -466,6 +531,8 @@ do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) const struct fsr_info *inf = fsr_info + (fsr & 15) + ((fsr & (1 << 10)) >> 6); struct siginfo info; + addr = fcse_mva_to_va(addr); + if (!inf->fn(addr, fsr, regs)) return; @@ -484,4 +551,3 @@ do_PrefetchAbort(unsigned long addr, struct pt_regs *regs) { do_translation_fault(addr, 0, regs); } - diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 9df507d..412a10a 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -14,6 +14,7 @@ #include <asm/cacheflush.h> #include <asm/system.h> #include <asm/tlbflush.h> +#include <asm/fcse.h> #include "mm.h" @@ -58,9 +59,11 @@ void flush_cache_mm(struct mm_struct *mm) void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { if (cache_is_vivt()) { - if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) - __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), - vma->vm_flags); + if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { + start = fcse_va_to_mva(vma->vm_mm, start) & PAGE_MASK; + end = PAGE_ALIGN(fcse_va_to_mva(vma->vm_mm, end)); + __cpuc_flush_user_range(start, end, vma->vm_flags); + } return; } @@ -78,7 +81,8 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig { if (cache_is_vivt()) { if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { - unsigned long addr = user_addr & PAGE_MASK; + unsigned long addr; + addr = fcse_va_to_mva(vma->vm_mm, user_addr) & PAGE_MASK; __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); } return; diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index e0f19ab..4da5e30 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -16,7 +16,11 @@ #include "mm.h" +#ifndef CONFIG_ARM_FCSE #define FIRST_KERNEL_PGD_NR (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD) +#else /* CONFIG_ARM_FCSE */ +#define FIRST_KERNEL_PGD_NR (MODULE_START / PGDIR_SIZE) +#endif /* CONFIG_ARM_FCSE */ /* * need to get a 16k page for level 1 @@ -26,6 +30,15 @@ pgd_t *get_pgd_slow(struct mm_struct *mm) pgd_t *new_pgd, *init_pgd; pmd_t *new_pmd, *init_pmd; pte_t *new_pte, *init_pte; +#ifdef CONFIG_ARM_FCSE + int pid; + + pid = fcse_pid_alloc(); + if (pid == -1) + goto no_pgd; + + mm->context.pid = pid << FCSE_PID_SHIFT; +#endif /* CONFIG_ARM_FCSE */ new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2); if (!new_pgd) @@ -43,11 +56,15 @@ pgd_t *get_pgd_slow(struct mm_struct *mm) clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t)); if (!vectors_high()) { + /* We can not use pgd_offset here since mm->pgd is not yet + initialized. */ + pgd_t *pgd = new_pgd + pgd_index(fcse_va_to_mva(mm, 0)); + /* * On ARM, first page must always be allocated since it * contains the machine vectors. */ - new_pmd = pmd_alloc(mm, new_pgd, 0); + new_pmd = pmd_alloc(mm, pgd, 0); if (!new_pmd) goto no_pmd; @@ -96,4 +113,7 @@ void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd) pmd_free(mm, pmd); free: free_pages((unsigned long) pgd, 2); +#ifdef CONFIG_ARM_FCSE + fcse_pid_free(mm->context.pid >> FCSE_PID_SHIFT); +#endif /* CONFIG_ARM_FCSE */ } diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 28cdb06..1f16a58 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -321,6 +321,10 @@ ENTRY(cpu_arm920_dcache_clean_area) ENTRY(cpu_arm920_switch_mm) #ifdef CONFIG_MMU mov ip, #0 +#ifdef CONFIG_ARM_FCSE + cmp r1, #0 + beq .LCnoflush +#endif #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache #else @@ -338,6 +342,9 @@ ENTRY(cpu_arm920_switch_mm) #endif mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache mcr p15, 0, ip, c7, c10, 4 @ drain WB +#ifdef CONFIG_ARM_FCSE +.LCnoflush: +#endif mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs #endif diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 4cd3316..edec79b 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -337,6 +337,10 @@ ENTRY(cpu_arm926_dcache_clean_area) ENTRY(cpu_arm926_switch_mm) #ifdef CONFIG_MMU mov ip, #0 +#ifdef CONFIG_ARM_FCSE + cmp r1, #0 + beq .LCnoflush +#endif #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache #else @@ -346,6 +350,9 @@ ENTRY(cpu_arm926_switch_mm) #endif mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache mcr p15, 0, ip, c7, c10, 4 @ drain WB +#ifdef CONFIG_ARM_FCSE +.LCnoflush: +#endif mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs #endif diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 2dd8527..2841857 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -417,9 +417,16 @@ ENTRY(cpu_xscale_dcache_clean_area) */ .align 5 ENTRY(cpu_xscale_switch_mm) +#ifdef CONFIG_ARM_FCSE + cmp r1, #0 + beq .LCnoflush +#endif clean_d_cache r1, r2 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer +#ifdef CONFIG_ARM_FCSE +.LCnoflush: +#endif mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs cpwait_ret lr, ip diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 759a97b..b4b3b08 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -15,6 +15,7 @@ #include <asm/glue.h> #include <asm/shmparam.h> +#include <asm/fcse.h> #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) @@ -339,16 +340,20 @@ static inline void flush_cache_mm(struct mm_struct *mm) static inline void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) + if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { + start = fcse_va_to_mva(vma->vm_mm,start); + end = fcse_va_to_mva(vma->vm_mm,end); __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), vma->vm_flags); + } } static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) { if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { - unsigned long addr = user_addr & PAGE_MASK; + unsigned long addr; + addr = fcse_va_to_mva(vma->vm_mm,user_addr) & PAGE_MASK; __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); } } @@ -379,8 +384,14 @@ extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, * Harvard caches are synchronised for the user space address range. * This is used for the ARM private sys_cacheflush system call. */ -#define flush_cache_user_range(vma,start,end) \ - __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) +#define flush_cache_user_range(vma,start,end) \ + ({ \ + struct mm_struct *_mm = (vma)->vm_mm; \ + unsigned long _start, _end; \ + _start = fcse_va_to_mva(_mm,start) & PAGE_MASK; \ + _end = PAGE_ALIGN(fcse_va_to_mva(_mm,end)); \ + __cpuc_coherent_user_range(_start, _end); \ + }) /* * Perform necessary cache operations to ensure that data previously @@ -417,7 +428,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma, extern void __flush_anon_page(struct vm_area_struct *vma, struct page *, unsigned long); if (PageAnon(page)) - __flush_anon_page(vma, page, vmaddr); + __flush_anon_page(vma, page, fcse_va_to_mva(vma->vm_mm,vmaddr)); } #define flush_dcache_mmap_lock(mapping) \ diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h index 3479de9..627daf3 100644 --- a/include/asm-arm/cpu-multi32.h +++ b/include/asm-arm/cpu-multi32.h @@ -52,7 +52,7 @@ extern struct processor { /* * Set the page table */ - void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm); + void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm, unsigned cacheflush); /* * Set a possibly extended PTE. Non-extended PTEs should * ignore 'ext'. @@ -66,4 +66,4 @@ extern struct processor { #define cpu_do_idle() processor._do_idle() #define cpu_dcache_clean_area(addr,sz) processor.dcache_clean_area(addr,sz) #define cpu_set_pte_ext(ptep,pte,ext) processor.set_pte_ext(ptep,pte,ext) -#define cpu_do_switch_mm(pgd,mm) processor.switch_mm(pgd,mm) +#define cpu_do_switch_mm(pgd,mm,flush) processor.switch_mm(pgd,mm,flush) diff --git a/include/asm-arm/cpu-single.h b/include/asm-arm/cpu-single.h index 0b120ee..e3a59f7 100644 --- a/include/asm-arm/cpu-single.h +++ b/include/asm-arm/cpu-single.h @@ -39,6 +39,6 @@ extern void cpu_proc_init(void); extern void cpu_proc_fin(void); extern int cpu_do_idle(void); extern void cpu_dcache_clean_area(void *, int); -extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); +extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm, unsigned cacheflush); extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext); extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); diff --git a/include/asm-arm/fcse.h b/include/asm-arm/fcse.h new file mode 100644 index 0000000..bfcd6ba --- /dev/null +++ b/include/asm-arm/fcse.h @@ -0,0 +1,79 @@ +/* + * Filename: include/asm-arm/pid.h + * Description: ARM Porcess ID (PID) includes for Fast Address Space Switching + * (FASS) in ARM Linux. + * Created: 14/10/2001 + * Changes: 19/02/2002 - Macros added. + * 03/08/2007 - Adapted to kernel 2.6.21 (ssm) + * Feb 2008 - Simplified a bit (rco) + * + * Copyright: (C) 2001, 2002 Adam Wiggins <awiggins@domain.hid> + * (C) 2007 Sebastian Smolorz <ssm@domain.hid> + * (C) 2008 Richard Co if (next) +chran + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of teh GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_PROC_PID_H +#define __ASM_PROC_PID_H + +#ifdef CONFIG_ARM_FCSE + +#define FCSE_PID_SHIFT 25 + +/* Size of PID relocation area */ +#define FCSE_PID_TASK_SIZE (1UL << FCSE_PID_SHIFT) + +/* Mask to get rid of PID from relocated address */ +#define FCSE_PID_MASK (FCSE_PID_TASK_SIZE - 1) + +#define fcse_tlb_mask(mm) ((mm)->context.cpu_tlb_mask) +#define fcse_cpu_set_vm_mask(cpu, mm) cpu_set(cpu, (mm)->cpu_vm_mask) +#define fcse_needs_flush(mm) ((mm)->context.mappings_needing_flush) + +/* Sets the CPU's PID Register */ +static inline void fcse_pid_set(unsigned long pid) +{ + __asm__ __volatile__("mcr p15, 0, %0, c13, c0, 0": /* */: "r" (pid)); +} + +/* Returns the state of the CPU's PID Register */ +static inline unsigned long fcse_pid_get(void) +{ + unsigned long pid; + __asm__ __volatile__("mrc p15, 0, %0, c13, c0, 0" : "=&r" (pid)); + return (pid & (~FCSE_PID_MASK)); +} + +static inline unsigned long fcse_mva_to_va(unsigned long mva) +{ + unsigned long pid = fcse_pid_get(); + if (pid && (pid == (mva & ~FCSE_PID_MASK))) { + return mva & FCSE_PID_MASK; + } + return mva; +} + +static inline unsigned long fcse_va_to_mva(struct mm_struct *mm, unsigned long va) +{ + if (va < FCSE_PID_TASK_SIZE) { + return mm->context.pid | va; + } + return va; +} + +int fcse_pid_alloc(void); +void fcse_pid_free(unsigned pid); + +#else /* CONFIG_ARM_FCSE */ +#define fcse_pid_set(pid) do { } while(0) +#define fcse_mva_to_va(x) (x) +#define fcse_va_to_mva(vma,x) (x) +#define fcse_tlb_mask(mm) ((mm)->cpu_vm_mask) +#define fcse_cpu_set_vm_mask(cpu, mm) do { } while(0) +#define fcse_needs_flush(mm) (1) +#endif + +#endif diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index 9ba4d71..bda4e74 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h @@ -34,14 +34,23 @@ * TASK_SIZE - the maximum size of a user space task. * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area */ +#ifdef CONFIG_ARM_FCSE +#define TASK_SIZE UL(0x02000000) +#define TASK_UNMAPPED_BASE UL(0x01000000) +#else #define TASK_SIZE UL(0xbf000000) #define TASK_UNMAPPED_BASE UL(0x40000000) #endif +#endif /* * The maximum size of a 26-bit user space task. */ +#ifdef CONFIG_ARM_FCSE +#define TASK_SIZE_26 UL(0x02000000) +#else #define TASK_SIZE_26 UL(0x04000000) +#endif /* * Page offset: 3GB diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h index 53099d4..b74d736 100644 --- a/include/asm-arm/mmu.h +++ b/include/asm-arm/mmu.h @@ -7,6 +7,11 @@ typedef struct { #ifdef CONFIG_CPU_HAS_ASID unsigned int id; #endif +#ifdef CONFIG_ARM_FCSE + unsigned long pid; + unsigned mappings_needing_flush; + cpumask_t cpu_tlb_mask; +#endif unsigned int kvm_seq; } mm_context_t; diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h index 6913d02..47339c2 100644 --- a/include/asm-arm/mmu_context.h +++ b/include/asm-arm/mmu_context.h @@ -17,6 +17,7 @@ #include <asm/cacheflush.h> #include <asm/proc-fns.h> #include <asm-generic/mm_hooks.h> +#include <asm/fcse.h> void __check_kvm_seq(struct mm_struct *mm); @@ -64,7 +65,15 @@ static inline void check_context(struct mm_struct *mm) __check_kvm_seq(mm); } -#define init_new_context(tsk,mm) 0 + +static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) +{ +#ifdef CONFIG_ARM_FCSE + cpus_clear(mm->context.cpu_tlb_mask); + mm->context.mappings_needing_flush = 0; +#endif /* CONFIG_ARM_FCSE */ + return 0; +} #endif @@ -97,11 +106,13 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, #ifdef CONFIG_MMU unsigned int cpu = smp_processor_id(); - if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) { + if (!cpu_test_and_set(cpu, fcse_tlb_mask(next)) || prev != next) { + fcse_cpu_set_vm_mask(cpu, next); check_context(next); - cpu_switch_mm(next->pgd, next); + fcse_pid_set(next->context.pid); + cpu_switch_mm(next->pgd, next, fcse_needs_flush(next)); if (cache_is_vivt()) - cpu_clear(cpu, prev->cpu_vm_mask); + cpu_clear(cpu, fcse_tlb_mask(prev)); } #endif } diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index 5571c13..701f458 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -344,10 +344,14 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) /* to find an entry in a page-table-directory */ #define pgd_index(addr) ((addr) >> PGDIR_SHIFT) -#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) +#define pgd_offset(mm, addr) \ + ({ \ + struct mm_struct *_mm = (mm); \ + (_mm->pgd + pgd_index(fcse_va_to_mva(_mm,(addr)))); \ + }) /* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(addr) pgd_offset(&init_mm, addr) +#define pgd_offset_k(addr) (init_mm.pgd+pgd_index(addr)) /* Find an entry in the second-level page table.. */ #define pmd_offset(dir, addr) ((pmd_t *)(dir)) diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h index 75ec760..37ba564 100644 --- a/include/asm-arm/proc-fns.h +++ b/include/asm-arm/proc-fns.h @@ -223,7 +223,8 @@ #ifdef CONFIG_MMU -#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm) +#define cpu_switch_mm(pgd,mm,cacheflush) \ + cpu_do_switch_mm(virt_to_phys(pgd),mm,(cacheflush)) #define cpu_get_pgd() \ ({ \ diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h index 8c6bc1b..98cd28f 100644 --- a/include/asm-arm/tlbflush.h +++ b/include/asm-arm/tlbflush.h @@ -158,6 +158,7 @@ #ifndef __ASSEMBLY__ #include <linux/sched.h> +#include <asm/fcse.h> struct cpu_tlb_fns { void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *); @@ -292,7 +293,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) if (tlb_flag(TLB_WB)) dsb(); - if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) { + if (cpu_isset(smp_processor_id(), fcse_tlb_mask(mm))) { if (tlb_flag(TLB_V3_FULL)) asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V4_U_FULL)) @@ -325,12 +326,13 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) const int zero = 0; const unsigned int __tlb_flag = __cpu_tlb_flags; - uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); + uaddr = (fcse_va_to_mva(vma->vm_mm,uaddr) & PAGE_MASK) + | ASID(vma->vm_mm); if (tlb_flag(TLB_WB)) dsb(); - if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { + if (cpu_isset(smp_processor_id(), fcse_tlb_mask(vma->vm_mm))) { if (tlb_flag(TLB_V3_PAGE)) asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc"); if (tlb_flag(TLB_V4_U_PAGE)) @@ -437,7 +439,15 @@ static inline void clean_pmd_entry(pmd_t *pmd) /* * Convert calls to our calling convention. */ -#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma) +#define local_flush_tlb_range(vma,start,end) \ + ({ \ + struct mm_struct *_mm = (vma)->vm_mm; \ + unsigned long _start, _end; \ + _start = fcse_va_to_mva(_mm, start); \ + _end = fcse_va_to_mva(_mm, end); \ + __cpu_flush_user_tlb_range(_start, _end, vma); \ + }) + #define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e) #ifndef CONFIG_SMP ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-10-02 8:44 ` Gilles Chanteperdrix @ 2008-10-02 14:54 ` Richard Cochran 2008-10-02 15:30 ` Gilles Chanteperdrix 2008-10-02 20:03 ` Gilles Chanteperdrix 2008-10-02 22:04 ` Bosko Radivojevic 1 sibling, 2 replies; 17+ messages in thread From: Richard Cochran @ 2008-10-02 14:54 UTC (permalink / raw) To: Gilles Chanteperdrix; +Cc: adeos-main > -----Original Message----- From: Gilles Chanteperdrix > > found the reason for the crash. The system seems to run stable now. > Here comes the patch. Great work! > Could you test it and confirm that there is no problem for you ? I back ported the patch to 2.6.21 and ran it on an NSLU. I did not see any trouble. I ran my three "production" user space programs and ran, at the same time: while [ 1 ]; do find /; cat /dev/mem > /dev/null; done Can you post your stress-testing script? I will test the new patch on my four other, different IXP boards. I will have to study the patch to understand what the trouble was. Perhaps you can explain it a bit? In any case, I found one huge error in the patch...you mangled my name ;) + * Copyright: (C) 2001, 2002 Adam Wiggins <awiggins@domain.hid> + * (C) 2007 Sebastian Smolorz <ssm@domain.hid> + * (C) 2008 Richard Co if (next) +chran + * Richard ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-10-02 14:54 ` Richard Cochran @ 2008-10-02 15:30 ` Gilles Chanteperdrix 2008-10-02 17:36 ` Gilles Chanteperdrix 2008-10-02 20:03 ` Gilles Chanteperdrix 1 sibling, 1 reply; 17+ messages in thread From: Gilles Chanteperdrix @ 2008-10-02 15:30 UTC (permalink / raw) To: Richard Cochran; +Cc: adeos-main Richard Cochran wrote: >> -----Original Message----- From: Gilles Chanteperdrix >> >> found the reason for the crash. The system seems to run stable now. >> Here comes the patch. > > Great work! > >> Could you test it and confirm that there is no problem for you ? > > I back ported the patch to 2.6.21 and ran it on an NSLU. I did not see > any trouble. I ran my three "production" user space programs and ran, > at the same time: > > while [ 1 ]; do find /; cat /dev/mem > /dev/null; done > > Can you post your stress-testing script? Well, I have not really stressed-test it, I have run a dd if=/dev/zero of=/dev/null, in parallel with a loop of ls -lR /, and launched the xenomai run script. I intend to make a real effort, and compile and run LTP, to avoid making myself ridiculous on the Linux arm kernel mailing list. I intend to ask if they are ready to include the patch into the mainline kernel if we make the effort of overcoming the 95 pids * 32 MiB limitation. > > I will test the new patch on my four other, different IXP boards. > > I will have to study the patch to understand what the trouble > was. Perhaps you can explain it a bit? One problem was the pid allocation: linux recycles pids faster than it recycles mm_structs, so by using the task_struct pid, we could have two mm_struct with the same pid at the same time. And since this allocation scheme was not using all pids with multi-threaded processes, I implemented a bitfield based PID allocation. Another problem was the way the mapping was built, I did not fully understand how the pmd_populate trick could work with such things as copy_page_range (which copies the pages at fork time, and should copy them automatically between different address spaces), and I did not like the way like there was two parallel mappings, so, I implemented something different: I made the pgd_offset macro "FCSE aware", and it turned out that it was sufficient to fix the page tables population completely. Something else I needed was that the cache flush do not rely on mm->cpu_vm_mask to flush. So, we basically wanted that the cpu bit be set in cpu_vm_mask unconditionnaly when the context is switched first to the new process, and not cleared in switch_to when the process is switched out. The most important cache flush which must happen is flush_cache_mm, which is called when a process dies, this is because since the pages are returned to the memory allocator, we do not want later cache line evictions to override these possibly reused pages. However, since we do flush the tlb, we want cpu_vm_mask not to be used by tlb flushing operations, so, I put a second cpumask_t in the mm context, which is conditionnaly used for tlb flushing operations instead of mm->cpu_vm_mask when CONFIG_ARM_FCSE is set, this mask being cleared by switch_to after the tlb is flushed. Another thing (which really is a quick hack in the current patch), is that we need cpu_do_switch_mm to do a full cache flush, when a process has a shared, writable, cached mapping, because of potential aliasing issues (we assume that applications are not stupid, and will not map a shared writable cacheable mapping if they are not really sharing it with other applications). So, cpu_do_switch_mm takes a second argument telling whether a cache flush should occur. What is a quick hack is the piece of code in do_mmap2 which checks if the mapping verifies the shared, writable, cacheabled constraints, but this check never happens when using mprotect, mremap, and munmap. We probably rather need architecture dependent hooks in the architecture-independent code, but I did not want to touch architecture-independent code. The problem which really blocked me for some time was two missing va_to_mvas in tlb user range flush operation (local_tlb_flush_range, or something). > > In any case, I found one huge error in the patch...you mangled my name > ;) > + * (C) 2008 Richard Co if (next) > +chran Sorry, must be "thumb on the touchpad" accident... :-) -- Gilles. ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-10-02 15:30 ` Gilles Chanteperdrix @ 2008-10-02 17:36 ` Gilles Chanteperdrix 0 siblings, 0 replies; 17+ messages in thread From: Gilles Chanteperdrix @ 2008-10-02 17:36 UTC (permalink / raw) To: Richard Cochran; +Cc: adeos-main Gilles Chanteperdrix wrote: > Something else I needed was that the cache flush do not rely on > mm->cpu_vm_mask to flush. So, we basically wanted that the cpu bit be > set in cpu_vm_mask unconditionnaly when the context is switched first to > the new process, and not cleared in switch_to when the process is > switched out. A side effect of this, is that va_to_mva had to be changed to use the pid of a given mm instead of using the current mm pid. Other cosmetic changes were to rename asm/pid.h asm/fcse.h, and prefix all fcse functions with fcse_ to avoid namespace pollution and so that it appears clearly in the source what fcse uses. -- Gilles. ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-10-02 14:54 ` Richard Cochran 2008-10-02 15:30 ` Gilles Chanteperdrix @ 2008-10-02 20:03 ` Gilles Chanteperdrix 2008-10-03 7:20 ` Richard Cochran 1 sibling, 1 reply; 17+ messages in thread From: Gilles Chanteperdrix @ 2008-10-02 20:03 UTC (permalink / raw) To: Richard Cochran; +Cc: adeos-main, Sebastian Smolorz [-- Attachment #1: Type: text/plain, Size: 437 bytes --] Richard Cochran wrote: > In any case, I found one huge error in the patch...you mangled my name > ;) Here is a better one, with this error fixed, as well as a fix in switch_mm which makes that now, we really do not flush the cache. Previous version flushed the cache at each switch due to an error in the register we checked. I have tested this version with Xenomai, and we get lower latencies (we gained 100us). -- Gilles. [-- Attachment #2: fcse.3.diff --] [-- Type: text/x-diff, Size: 21857 bytes --] diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index ad455ff..4481a30 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -10,6 +10,7 @@ obj-y := compat.o entry-armv.o entry-common.o irq.o \ process.o ptrace.o setup.o signal.o \ sys_arm.o stacktrace.o time.o traps.o +obj-$(CONFIG_ARM_FCSE) += fcse.o obj-$(CONFIG_ISA_DMA_API) += dma.o obj-$(CONFIG_ARCH_ACORN) += ecard.o obj-$(CONFIG_FIQ) += fiq.o diff --git a/arch/arm/kernel/fcse.c b/arch/arm/kernel/fcse.c new file mode 100644 index 0000000..1900a79 --- /dev/null +++ b/arch/arm/kernel/fcse.c @@ -0,0 +1,37 @@ +#include <linux/bitops.h> +#include <linux/memory.h> +#include <linux/spinlock.h> +#include <linux/bitops.h> +#include <asm/fcse.h> + +#define MAX_PID (MODULE_START / FCSE_PID_TASK_SIZE) +#define PIDS_LONGS (MAX_PID + 8 * sizeof(long) - 1) / (8 * sizeof(long)) + +static spinlock_t fcse_lock = SPIN_LOCK_UNLOCKED; +static unsigned long fcse_pids_bits[PIDS_LONGS]; + +int fcse_pid_alloc(void) +{ + unsigned long flags; + unsigned bit; + + spin_lock_irqsave(&fcse_lock, flags); + bit = find_first_zero_bit(fcse_pids_bits, MAX_PID); + if (bit == MAX_PID) { + spin_unlock(&fcse_lock); + return -1; + } + set_bit(bit, fcse_pids_bits); + spin_unlock_irqrestore(&fcse_lock, flags); + + return bit; +} + +void fcse_pid_free(unsigned pid) +{ + unsigned long flags; + + spin_lock_irqsave(&fcse_lock, flags); + pid = test_and_clear_bit(pid, fcse_pids_bits); + spin_unlock_irqrestore(&fcse_lock, flags); +} diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index eefae1d..b13d8a5 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -32,6 +32,7 @@ #include <asm/processor.h> #include <asm/tlbflush.h> #include <asm/ptrace.h> +#include <asm/fcse.h> /* * bitmask of present and online CPUs. @@ -736,14 +737,14 @@ void flush_tlb_all(void) void flush_tlb_mm(struct mm_struct *mm) { - cpumask_t mask = mm->cpu_vm_mask; + cpumask_t mask = fcse_tlb_mask(mm); on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, 1, mask); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) { - cpumask_t mask = vma->vm_mm->cpu_vm_mask; + cpumask_t mask = fcse_tlb_mask(vma->vm_mm); struct tlb_args ta; ta.ta_vma = vma; @@ -764,7 +765,7 @@ void flush_tlb_kernel_page(unsigned long kaddr) void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - cpumask_t mask = vma->vm_mm->cpu_vm_mask; + cpumask_t mask = fcse_tlb_mask(vma->vm_mm); struct tlb_args ta; ta.ta_vma = vma; diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c index 0128687..b8d1605 100644 --- a/arch/arm/kernel/sys_arm.c +++ b/arch/arm/kernel/sys_arm.c @@ -61,7 +61,18 @@ inline long do_mmap2( if (file) fput(file); +#ifdef CONFIG_ARM_FCSE + /* FIXME, this really sucks, and we should really recheck in mremap, + mprotect, and munmap */ + if (likely((unsigned) error < (unsigned)(-4096)) + && (flags & MAP_SHARED) && (prot & PROT_WRITE)) { + struct vm_area_struct *vma = find_vma(current->mm, error); + if (vma->vm_page_prot & (L_PTE_CACHEABLE | L_PTE_BUFFERABLE)) + ++current->mm->context.mappings_needing_flush; + } +#endif out: + return error; } diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 33ed048..6c40ac0 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -716,3 +716,10 @@ config CACHE_L2X0 select OUTER_CACHE help This option enables the L2x0 PrimeCell. + +config ARM_FCSE + bool "Fast Context Switch Extension (EXPERIMENTAL)" + depends on EXPERIMENTAL + default n + help + Say Y here to enable the ARM FCSE. If unsure, say N. diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 28ad7ab..b23d3c9 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c @@ -13,11 +13,13 @@ #include <linux/mm.h> #include <linux/init.h> #include <linux/kprobes.h> +#include <linux/kallsyms.h> #include <asm/system.h> #include <asm/pgtable.h> #include <asm/tlbflush.h> #include <asm/uaccess.h> +#include <asm/fcse.h> #include "fault.h" @@ -55,6 +57,10 @@ void show_pte(struct mm_struct *mm, unsigned long addr) if (!mm) mm = &init_mm; +#ifdef CONFIG_ARM_FCSE + printk(KERN_ALERT "fcse pid: %ld, 0x%08lx\n", + mm->context.pid >> FCSE_PID_SHIFT, mm->context.pid); +#endif /* CONFIG_ARM_FCSE */ printk(KERN_ALERT "pgd = %p\n", mm->pgd); pgd = pgd_offset(mm, addr); printk(KERN_ALERT "[%08lx] *pgd=%08lx", addr, pgd_val(*pgd)); @@ -466,6 +472,8 @@ do_DataAbort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) const struct fsr_info *inf = fsr_info + (fsr & 15) + ((fsr & (1 << 10)) >> 6); struct siginfo info; + addr = fcse_mva_to_va(addr); + if (!inf->fn(addr, fsr, regs)) return; @@ -484,4 +492,3 @@ do_PrefetchAbort(unsigned long addr, struct pt_regs *regs) { do_translation_fault(addr, 0, regs); } - diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 9df507d..412a10a 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -14,6 +14,7 @@ #include <asm/cacheflush.h> #include <asm/system.h> #include <asm/tlbflush.h> +#include <asm/fcse.h> #include "mm.h" @@ -58,9 +59,11 @@ void flush_cache_mm(struct mm_struct *mm) void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { if (cache_is_vivt()) { - if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) - __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), - vma->vm_flags); + if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { + start = fcse_va_to_mva(vma->vm_mm, start) & PAGE_MASK; + end = PAGE_ALIGN(fcse_va_to_mva(vma->vm_mm, end)); + __cpuc_flush_user_range(start, end, vma->vm_flags); + } return; } @@ -78,7 +81,8 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig { if (cache_is_vivt()) { if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { - unsigned long addr = user_addr & PAGE_MASK; + unsigned long addr; + addr = fcse_va_to_mva(vma->vm_mm, user_addr) & PAGE_MASK; __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); } return; diff --git a/arch/arm/mm/pgd.c b/arch/arm/mm/pgd.c index e0f19ab..4da5e30 100644 --- a/arch/arm/mm/pgd.c +++ b/arch/arm/mm/pgd.c @@ -16,7 +16,11 @@ #include "mm.h" +#ifndef CONFIG_ARM_FCSE #define FIRST_KERNEL_PGD_NR (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD) +#else /* CONFIG_ARM_FCSE */ +#define FIRST_KERNEL_PGD_NR (MODULE_START / PGDIR_SIZE) +#endif /* CONFIG_ARM_FCSE */ /* * need to get a 16k page for level 1 @@ -26,6 +30,15 @@ pgd_t *get_pgd_slow(struct mm_struct *mm) pgd_t *new_pgd, *init_pgd; pmd_t *new_pmd, *init_pmd; pte_t *new_pte, *init_pte; +#ifdef CONFIG_ARM_FCSE + int pid; + + pid = fcse_pid_alloc(); + if (pid == -1) + goto no_pgd; + + mm->context.pid = pid << FCSE_PID_SHIFT; +#endif /* CONFIG_ARM_FCSE */ new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2); if (!new_pgd) @@ -43,11 +56,15 @@ pgd_t *get_pgd_slow(struct mm_struct *mm) clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t)); if (!vectors_high()) { + /* We can not use pgd_offset here since mm->pgd is not yet + initialized. */ + pgd_t *pgd = new_pgd + pgd_index(fcse_va_to_mva(mm, 0)); + /* * On ARM, first page must always be allocated since it * contains the machine vectors. */ - new_pmd = pmd_alloc(mm, new_pgd, 0); + new_pmd = pmd_alloc(mm, pgd, 0); if (!new_pmd) goto no_pmd; @@ -96,4 +113,7 @@ void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd) pmd_free(mm, pmd); free: free_pages((unsigned long) pgd, 2); +#ifdef CONFIG_ARM_FCSE + fcse_pid_free(mm->context.pid >> FCSE_PID_SHIFT); +#endif /* CONFIG_ARM_FCSE */ } diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 28cdb06..2454d0b 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -321,6 +321,10 @@ ENTRY(cpu_arm920_dcache_clean_area) ENTRY(cpu_arm920_switch_mm) #ifdef CONFIG_MMU mov ip, #0 +#ifdef CONFIG_ARM_FCSE + cmp r2, #0 + beq .LCnoflush +#endif #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache #else @@ -338,6 +342,9 @@ ENTRY(cpu_arm920_switch_mm) #endif mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache mcr p15, 0, ip, c7, c10, 4 @ drain WB +#ifdef CONFIG_ARM_FCSE +.LCnoflush: +#endif mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs #endif diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index 4cd3316..ca7f4ee 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -337,6 +337,10 @@ ENTRY(cpu_arm926_dcache_clean_area) ENTRY(cpu_arm926_switch_mm) #ifdef CONFIG_MMU mov ip, #0 +#ifdef CONFIG_ARM_FCSE + cmp r2, #0 + beq .LCnoflush +#endif #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache #else @@ -346,6 +350,9 @@ ENTRY(cpu_arm926_switch_mm) #endif mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache mcr p15, 0, ip, c7, c10, 4 @ drain WB +#ifdef CONFIG_ARM_FCSE +.LCnoflush: +#endif mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs #endif diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 2dd8527..c101e5d 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -417,9 +417,16 @@ ENTRY(cpu_xscale_dcache_clean_area) */ .align 5 ENTRY(cpu_xscale_switch_mm) +#ifdef CONFIG_ARM_FCSE + cmp r2, #0 + beq .LCnoflush +#endif clean_d_cache r1, r2 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer +#ifdef CONFIG_ARM_FCSE +.LCnoflush: +#endif mcr p15, 0, r0, c2, c0, 0 @ load page table pointer mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs cpwait_ret lr, ip diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h index 759a97b..b4b3b08 100644 --- a/include/asm-arm/cacheflush.h +++ b/include/asm-arm/cacheflush.h @@ -15,6 +15,7 @@ #include <asm/glue.h> #include <asm/shmparam.h> +#include <asm/fcse.h> #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) @@ -339,16 +340,20 @@ static inline void flush_cache_mm(struct mm_struct *mm) static inline void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) { - if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) + if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { + start = fcse_va_to_mva(vma->vm_mm,start); + end = fcse_va_to_mva(vma->vm_mm,end); __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), vma->vm_flags); + } } static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) { if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { - unsigned long addr = user_addr & PAGE_MASK; + unsigned long addr; + addr = fcse_va_to_mva(vma->vm_mm,user_addr) & PAGE_MASK; __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); } } @@ -379,8 +384,14 @@ extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, * Harvard caches are synchronised for the user space address range. * This is used for the ARM private sys_cacheflush system call. */ -#define flush_cache_user_range(vma,start,end) \ - __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) +#define flush_cache_user_range(vma,start,end) \ + ({ \ + struct mm_struct *_mm = (vma)->vm_mm; \ + unsigned long _start, _end; \ + _start = fcse_va_to_mva(_mm,start) & PAGE_MASK; \ + _end = PAGE_ALIGN(fcse_va_to_mva(_mm,end)); \ + __cpuc_coherent_user_range(_start, _end); \ + }) /* * Perform necessary cache operations to ensure that data previously @@ -417,7 +428,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma, extern void __flush_anon_page(struct vm_area_struct *vma, struct page *, unsigned long); if (PageAnon(page)) - __flush_anon_page(vma, page, vmaddr); + __flush_anon_page(vma, page, fcse_va_to_mva(vma->vm_mm,vmaddr)); } #define flush_dcache_mmap_lock(mapping) \ diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h index 3479de9..627daf3 100644 --- a/include/asm-arm/cpu-multi32.h +++ b/include/asm-arm/cpu-multi32.h @@ -52,7 +52,7 @@ extern struct processor { /* * Set the page table */ - void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm); + void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm, unsigned cacheflush); /* * Set a possibly extended PTE. Non-extended PTEs should * ignore 'ext'. @@ -66,4 +66,4 @@ extern struct processor { #define cpu_do_idle() processor._do_idle() #define cpu_dcache_clean_area(addr,sz) processor.dcache_clean_area(addr,sz) #define cpu_set_pte_ext(ptep,pte,ext) processor.set_pte_ext(ptep,pte,ext) -#define cpu_do_switch_mm(pgd,mm) processor.switch_mm(pgd,mm) +#define cpu_do_switch_mm(pgd,mm,flush) processor.switch_mm(pgd,mm,flush) diff --git a/include/asm-arm/cpu-single.h b/include/asm-arm/cpu-single.h index 0b120ee..e3a59f7 100644 --- a/include/asm-arm/cpu-single.h +++ b/include/asm-arm/cpu-single.h @@ -39,6 +39,6 @@ extern void cpu_proc_init(void); extern void cpu_proc_fin(void); extern int cpu_do_idle(void); extern void cpu_dcache_clean_area(void *, int); -extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); +extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm, unsigned cacheflush); extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext); extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); diff --git a/include/asm-arm/fcse.h b/include/asm-arm/fcse.h new file mode 100644 index 0000000..c9ee051 --- /dev/null +++ b/include/asm-arm/fcse.h @@ -0,0 +1,78 @@ +/* + * Filename: include/asm-arm/fcse.h + * Description: ARM Process ID (PID) includes for Fast Address Space Switching + * (FASS) in ARM Linux. + * Created: 14/10/2001 + * Changes: 19/02/2002 - Macros added. + * 03/08/2007 - Adapted to kernel 2.6.21 (ssm) + * Feb 2008 - Simplified a bit (rco) + * + * Copyright: (C) 2001, 2002 Adam Wiggins <awiggins@domain.hid> + * (C) 2007 Sebastian Smolorz <ssm@domain.hid> + * (C) 2008 Richard Cochran + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of teh GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_ARM_FCSE_H +#define __ASM_ARM_FCSE_H + +#ifdef CONFIG_ARM_FCSE + +#define FCSE_PID_SHIFT 25 + +/* Size of PID relocation area */ +#define FCSE_PID_TASK_SIZE (1UL << FCSE_PID_SHIFT) + +/* Mask to get rid of PID from relocated address */ +#define FCSE_PID_MASK (FCSE_PID_TASK_SIZE - 1) + +#define fcse_tlb_mask(mm) ((mm)->context.cpu_tlb_mask) +#define fcse_cpu_set_vm_mask(cpu, mm) cpu_set(cpu, (mm)->cpu_vm_mask) +#define fcse_needs_flush(mm) ((mm)->context.mappings_needing_flush) + +/* Sets the CPU's PID Register */ +static inline void fcse_pid_set(unsigned long pid) +{ + __asm__ __volatile__("mcr p15, 0, %0, c13, c0, 0": /* */: "r" (pid)); +} + +/* Returns the state of the CPU's PID Register */ +static inline unsigned long fcse_pid_get(void) +{ + unsigned long pid; + __asm__ __volatile__("mrc p15, 0, %0, c13, c0, 0" : "=&r" (pid)); + return (pid & (~FCSE_PID_MASK)); +} + +static inline unsigned long fcse_mva_to_va(unsigned long mva) +{ + unsigned long pid = fcse_pid_get(); + if (pid && (pid == (mva & ~FCSE_PID_MASK))) { + return mva & FCSE_PID_MASK; + } + return mva; +} + +static inline unsigned long fcse_va_to_mva(struct mm_struct *mm, unsigned long va) +{ + if (va < FCSE_PID_TASK_SIZE) { + return mm->context.pid | va; + } + return va; +} + +int fcse_pid_alloc(void); +void fcse_pid_free(unsigned pid); + +#else /* CONFIG_ARM_FCSE */ +#define fcse_pid_set(pid) do { } while(0) +#define fcse_mva_to_va(x) (x) +#define fcse_va_to_mva(vma,x) (x) +#define fcse_tlb_mask(mm) ((mm)->cpu_vm_mask) +#define fcse_cpu_set_vm_mask(cpu, mm) do { } while(0) +#define fcse_needs_flush(mm) (1) +#endif + +#endif /* __ASM_ARM_FCSE_H */ diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index 9ba4d71..bda4e74 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h @@ -34,14 +34,23 @@ * TASK_SIZE - the maximum size of a user space task. * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area */ +#ifdef CONFIG_ARM_FCSE +#define TASK_SIZE UL(0x02000000) +#define TASK_UNMAPPED_BASE UL(0x01000000) +#else #define TASK_SIZE UL(0xbf000000) #define TASK_UNMAPPED_BASE UL(0x40000000) #endif +#endif /* * The maximum size of a 26-bit user space task. */ +#ifdef CONFIG_ARM_FCSE +#define TASK_SIZE_26 UL(0x02000000) +#else #define TASK_SIZE_26 UL(0x04000000) +#endif /* * Page offset: 3GB diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h index 53099d4..b74d736 100644 --- a/include/asm-arm/mmu.h +++ b/include/asm-arm/mmu.h @@ -7,6 +7,11 @@ typedef struct { #ifdef CONFIG_CPU_HAS_ASID unsigned int id; #endif +#ifdef CONFIG_ARM_FCSE + unsigned long pid; + unsigned mappings_needing_flush; + cpumask_t cpu_tlb_mask; +#endif unsigned int kvm_seq; } mm_context_t; diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h index 6913d02..47339c2 100644 --- a/include/asm-arm/mmu_context.h +++ b/include/asm-arm/mmu_context.h @@ -17,6 +17,7 @@ #include <asm/cacheflush.h> #include <asm/proc-fns.h> #include <asm-generic/mm_hooks.h> +#include <asm/fcse.h> void __check_kvm_seq(struct mm_struct *mm); @@ -64,7 +65,15 @@ static inline void check_context(struct mm_struct *mm) __check_kvm_seq(mm); } -#define init_new_context(tsk,mm) 0 + +static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) +{ +#ifdef CONFIG_ARM_FCSE + cpus_clear(mm->context.cpu_tlb_mask); + mm->context.mappings_needing_flush = 0; +#endif /* CONFIG_ARM_FCSE */ + return 0; +} #endif @@ -97,11 +106,13 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, #ifdef CONFIG_MMU unsigned int cpu = smp_processor_id(); - if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) { + if (!cpu_test_and_set(cpu, fcse_tlb_mask(next)) || prev != next) { + fcse_cpu_set_vm_mask(cpu, next); check_context(next); - cpu_switch_mm(next->pgd, next); + fcse_pid_set(next->context.pid); + cpu_switch_mm(next->pgd, next, fcse_needs_flush(next)); if (cache_is_vivt()) - cpu_clear(cpu, prev->cpu_vm_mask); + cpu_clear(cpu, fcse_tlb_mask(prev)); } #endif } diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index 5571c13..701f458 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -344,10 +344,14 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) /* to find an entry in a page-table-directory */ #define pgd_index(addr) ((addr) >> PGDIR_SHIFT) -#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) +#define pgd_offset(mm, addr) \ + ({ \ + struct mm_struct *_mm = (mm); \ + (_mm->pgd + pgd_index(fcse_va_to_mva(_mm,(addr)))); \ + }) /* to find an entry in a kernel page-table-directory */ -#define pgd_offset_k(addr) pgd_offset(&init_mm, addr) +#define pgd_offset_k(addr) (init_mm.pgd+pgd_index(addr)) /* Find an entry in the second-level page table.. */ #define pmd_offset(dir, addr) ((pmd_t *)(dir)) diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h index 75ec760..37ba564 100644 --- a/include/asm-arm/proc-fns.h +++ b/include/asm-arm/proc-fns.h @@ -223,7 +223,8 @@ #ifdef CONFIG_MMU -#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm) +#define cpu_switch_mm(pgd,mm,cacheflush) \ + cpu_do_switch_mm(virt_to_phys(pgd),mm,(cacheflush)) #define cpu_get_pgd() \ ({ \ diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h index 8c6bc1b..98cd28f 100644 --- a/include/asm-arm/tlbflush.h +++ b/include/asm-arm/tlbflush.h @@ -158,6 +158,7 @@ #ifndef __ASSEMBLY__ #include <linux/sched.h> +#include <asm/fcse.h> struct cpu_tlb_fns { void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *); @@ -292,7 +293,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) if (tlb_flag(TLB_WB)) dsb(); - if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) { + if (cpu_isset(smp_processor_id(), fcse_tlb_mask(mm))) { if (tlb_flag(TLB_V3_FULL)) asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); if (tlb_flag(TLB_V4_U_FULL)) @@ -325,12 +326,13 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) const int zero = 0; const unsigned int __tlb_flag = __cpu_tlb_flags; - uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); + uaddr = (fcse_va_to_mva(vma->vm_mm,uaddr) & PAGE_MASK) + | ASID(vma->vm_mm); if (tlb_flag(TLB_WB)) dsb(); - if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { + if (cpu_isset(smp_processor_id(), fcse_tlb_mask(vma->vm_mm))) { if (tlb_flag(TLB_V3_PAGE)) asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc"); if (tlb_flag(TLB_V4_U_PAGE)) @@ -437,7 +439,15 @@ static inline void clean_pmd_entry(pmd_t *pmd) /* * Convert calls to our calling convention. */ -#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma) +#define local_flush_tlb_range(vma,start,end) \ + ({ \ + struct mm_struct *_mm = (vma)->vm_mm; \ + unsigned long _start, _end; \ + _start = fcse_va_to_mva(_mm, start); \ + _end = fcse_va_to_mva(_mm, end); \ + __cpu_flush_user_tlb_range(_start, _end, vma); \ + }) + #define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e) #ifndef CONFIG_SMP ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-10-02 20:03 ` Gilles Chanteperdrix @ 2008-10-03 7:20 ` Richard Cochran 0 siblings, 0 replies; 17+ messages in thread From: Richard Cochran @ 2008-10-03 7:20 UTC (permalink / raw) To: Gilles Chanteperdrix; +Cc: adeos-main, Sebastian Smolorz Gilles, I have found that on both 2.6.21 and 2.6.26, I need to add an include of <linux/sched.h> to fcse.h in order to get the definition of struct mm_struct. Richard > -----Original Message----- > From: Gilles Chanteperdrix > Sent: Thursday, October 02, 2008 10:04 PM > Subject: Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE > > > Richard Cochran wrote: > > In any case, I found one huge error in the patch...you > mangled my name > > ;) > > Here is a better one, with this error fixed, as well as a fix in > switch_mm which makes that now, we really do not flush the cache. > Previous version flushed the cache at each switch due to an > error in the > register we checked. > > I have tested this version with Xenomai, and we get lower > latencies (we > gained 100us). > > -- > Gilles. > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-10-02 8:44 ` Gilles Chanteperdrix 2008-10-02 14:54 ` Richard Cochran @ 2008-10-02 22:04 ` Bosko Radivojevic 2008-10-02 22:34 ` Gilles Chanteperdrix 1 sibling, 1 reply; 17+ messages in thread From: Bosko Radivojevic @ 2008-10-02 22:04 UTC (permalink / raw) To: Gilles Chanteperdrix, Richard Cochran, adeos-main Great! I'll test the patch as soon as possible, but, unfortunately, not before 12th October. On 10/2/08, Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org> wrote: > Gilles Chanteperdrix wrote: >> Gilles Chanteperdrix wrote: >>> Gilles Chanteperdrix wrote: >>>> Richard Cochran wrote: >>>>> I posted this patch today on linux-arm-kernel, but I repeat it >>>>> here because there does not seem to be too much interest on that >>>>> list for the ARM FCSE. >>>>> >>>>> I also tried to combine this patch with ipipe for kernel 2.6.20 >>>>> running on the Intel IXDP465, but after booting I soon get a BUG. >>>>> >>>>> Anyhow, perhaps the ARM people might take a look at combining >>>>> ipipe with FCSE... >>>> Ok. Six monthes later, I finally gave a try to your patch on at91rm9200, >>>> which supports FCSE as well. >>>> >>>> When booting, I get random segmentation faults (either with or without >>>> the I-pipe), assertion which fails in glibc, and such things. >>> A small update: I get the same random failures with a vanilla kernel >>> (without I-pipe patch at all). >>> >>> I will now investigate pmd_populate. >> >> Hi Richard, >> >> I changed a few bits here and there in your patch, but I believe the >> biggest problem was that Linux seem to recycle pids faster than it >> recycles mm_struct, so we ended up with processes sharing the same >> space, and since the pid allocation mechanism was a bit too naive for >> multi-threaded applications, I changed it to a bitfield based solution. >> I now have an FCSE kernel which seems much more stable (and without the >> double mapping either). This is the good news. >> >> The bad news is that I still get mysterious crashes. So, will now >> investigate. > > Hi, > > found the reason for the crash. The system seems to run stable now. > Here comes the patch. > > Could you test it and confirm that there is no problem for you ? > Bosko: could you test it for arm926 ? I made the needed change in > arch/arm/mm/proc-arm926.S, but did not check it yet. > The patch is for vanilla Linux, I did not retest it with Xenomai yet > (though I tested the previous version with the random crashes, and > observed a 200us user-space latency instead of the usual 300us). > > Regards. > > -- > Gilles. > -- Sent from Gmail for mobile | mobile.google.com ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-10-02 22:04 ` Bosko Radivojevic @ 2008-10-02 22:34 ` Gilles Chanteperdrix 2008-10-03 1:57 ` Philippe Gerum 0 siblings, 1 reply; 17+ messages in thread From: Gilles Chanteperdrix @ 2008-10-02 22:34 UTC (permalink / raw) To: Bosko Radivojevic; +Cc: adeos-main Bosko Radivojevic wrote: > Great! I'll test the patch as soon as possible, but, unfortunately, > not before 12th October. Ok. No problem, I have a 926 now, so should be able to test it. And we merged the FCSE patch with the I-pipe patch, so the next release of the I-pipe patch should allow using FCSE. -- Gilles. ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Adeos-main] FW: [PATCH] repost: ARM FCSE 2008-10-02 22:34 ` Gilles Chanteperdrix @ 2008-10-03 1:57 ` Philippe Gerum 0 siblings, 0 replies; 17+ messages in thread From: Philippe Gerum @ 2008-10-03 1:57 UTC (permalink / raw) To: Gilles Chanteperdrix; +Cc: adeos-main Gilles Chanteperdrix wrote: > Bosko Radivojevic wrote: >> Great! I'll test the patch as soon as possible, but, unfortunately, >> not before 12th October. > > Ok. No problem, I have a 926 now, so should be able to test it. And we > merged the FCSE patch with the I-pipe patch, so the next release of the > I-pipe patch should allow using FCSE. > http://download.gna.org/adeos/patches/v2.6/arm/adeos-ipipe-2.6.26-arm-1.11-00.patch -- Philippe. ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2008-10-03 7:20 UTC | newest] Thread overview: 17+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2008-03-07 16:19 [Adeos-main] FW: [PATCH] repost: ARM FCSE Richard Cochran 2008-03-07 16:31 ` Gilles Chanteperdrix 2008-09-21 15:52 ` Gilles Chanteperdrix 2008-09-21 16:30 ` Gilles Chanteperdrix 2008-09-23 18:32 ` Gilles Chanteperdrix 2008-09-24 5:47 ` Richard Cochran 2008-09-24 7:38 ` Gilles Chanteperdrix 2008-09-27 17:53 ` Gilles Chanteperdrix 2008-10-02 8:44 ` Gilles Chanteperdrix 2008-10-02 14:54 ` Richard Cochran 2008-10-02 15:30 ` Gilles Chanteperdrix 2008-10-02 17:36 ` Gilles Chanteperdrix 2008-10-02 20:03 ` Gilles Chanteperdrix 2008-10-03 7:20 ` Richard Cochran 2008-10-02 22:04 ` Bosko Radivojevic 2008-10-02 22:34 ` Gilles Chanteperdrix 2008-10-03 1:57 ` Philippe Gerum
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