Fwd: x86: HPET: read back compare register before reading counter

Fwd: x86: HPET: read back compare register before reading counter

[Jan Beulich]

Wouldn't this be needed in Xen, too? On top of this, there is a patch
converting the WARN_ON() to WARN_ON_ONCE(), and in our SLE11 tree we
have an additional McCreary specific fix that actually does a 'pre-read' prior
to the WARN_ON_ONCE() as on that platform the first read apparently returns
the comparator value from before the last write. It is however being reported
that the issue seen here isn't present in 2.6.28 anymore, which seems
suspicious to me.

See http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=72d43d9bc9210d24d09202eaf219eac09e17b339.

Jan

From: Thomas Gleixner <tglx@linutronix.de>

After fixing the u32 thinko I sill had occasional hickups on ATI chipsets
with small deltas. There seems to be a delay between writing the compare
register and the transffer to the internal register which triggers the
interrupt. Reading back the value makes sure, that it hit the internal
match register befor we compare against the counter value.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---

diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 801497a..73deaff 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -278,6 +278,13 @@ static int hpet_legacy_next_event(unsigned long delta,
 	cnt += (u32) delta;
 	hpet_writel(cnt, HPET_T0_CMP);
 
+	/*
+	 * We need to read back the CMP register to make sure that
+	 * what we wrote hit the chip before we compare it to the
+	 * counter.
+	 */
+	WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt);
+
 	return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
 }
 

RE: Fwd: x86: HPET: read back compare register before reading counter

[Tian, Kevin]

I think it required, but as you said the weirdness is how that may be 
affected by software. We'll do some experiment here.

Thanks,
Kevin

>From: Jan Beulich
>Sent: Friday, November 21, 2008 9:44 PM
>
>Wouldn't this be needed in Xen, too? On top of this, there is a patch
>converting the WARN_ON() to WARN_ON_ONCE(), and in our SLE11 tree we
>have an additional McCreary specific fix that actually does a 
>'pre-read' prior
>to the WARN_ON_ONCE() as on that platform the first read 
>apparently returns
>the comparator value from before the last write. It is however 
>being reported
>that the issue seen here isn't present in 2.6.28 anymore, which seems
>suspicious to me.
>
>See 
>http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.gi
>t;a=commitdiff;h=72d43d9bc9210d24d09202eaf219eac09e17b339.
>
>Jan
>
>From: Thomas Gleixner <tglx@linutronix.de>
>
>After fixing the u32 thinko I sill had occasional hickups on 
>ATI chipsets
>with small deltas. There seems to be a delay between writing 
>the compare
>register and the transffer to the internal register which triggers the
>interrupt. Reading back the value makes sure, that it hit the internal
>match register befor we compare against the counter value.
>
>Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
>---
>
>diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
>index 801497a..73deaff 100644
>--- a/arch/x86/kernel/hpet.c
>+++ b/arch/x86/kernel/hpet.c
>@@ -278,6 +278,13 @@ static int 
>hpet_legacy_next_event(unsigned long delta,
> 	cnt += (u32) delta;
> 	hpet_writel(cnt, HPET_T0_CMP);
> 
>+	/*
>+	 * We need to read back the CMP register to make sure that
>+	 * what we wrote hit the chip before we compare it to the
>+	 * counter.
>+	 */
>+	WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt);
>+
> 	return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 
>? -ETIME : 0;
> }
> 
>
>
>
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