From: "Jan Beulich" <jbeulich@novell.com>
To: Keir Fraser <keir.fraser@eu.citrix.com>,
Dexuan Cui <dexuan.cui@intel.com>,
Dan Magenheimer <dan.magenheimer@oracle.com>
Cc: xen-devel@lists.xensource.com
Subject: RE: [PATCH] x86: add SSE-based copy_page()
Date: Tue, 13 Jan 2009 08:31:09 +0000 [thread overview]
Message-ID: <496C5F5D.76E4.0078.0@novell.com> (raw)
>>> Dan Magenheimer <dan.magenheimer@oracle.com> 13.01.09 00:29 >>>
>I'm guessing the gcc optimizer for the memcpy code was tuned
>for an Intel pipeline... Jan, were you measuring on an
>AMD processor?
Oh, actually my previous reply was without pushing my thinking fully back
to what I was doing (and measuring) back then. I really measured on quad
core Xeons, as what I was looking at were the highmem helpers. Pretty
likely this almost exclusively covered the cold cache (all levels) case, but I
also think this is the most likely scenario.
Jan
next reply other threads:[~2009-01-13 8:31 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-01-13 8:31 Jan Beulich [this message]
-- strict thread matches above, loose matches on Subject: below --
2008-11-12 9:37 [PATCH] x86: add SSE-based copy_page() Jan Beulich
2008-11-12 14:51 ` Dan Magenheimer
2008-11-12 15:01 ` Jan Beulich
2008-11-12 17:17 ` Dan Magenheimer
2008-11-13 8:37 ` Jan Beulich
2008-11-13 23:41 ` Dan Magenheimer
2008-11-14 3:08 ` Cui, Dexuan
2008-11-14 14:10 ` Dan Magenheimer
2008-11-14 14:16 ` Keir Fraser
2008-11-19 20:24 ` Dan Magenheimer
2008-11-19 21:21 ` Keir Fraser
2008-11-20 8:46 ` Jan Beulich
2009-01-12 23:29 ` Dan Magenheimer
2009-01-13 8:13 ` Keir Fraser
2009-01-13 8:34 ` Jan Beulich
2009-01-13 8:27 ` Jan Beulich
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