Re: Marvell 88E609x switch?

[Gary Thomas <gary@mlbassoc.com>]

Lennert Buytenhek wrote:
> On Mon, Mar 02, 2009 at 11:56:22AM +0100, Jesper Dangaard Brouer wrote:
> 
>>> The main conclusion so far is that this write (net/dsa/mv88e6131.c):
>>>
>>> 	/*
>>> 	 * MAC Forcing register: don't force link, speed, duplex
>>> 	 * or flow control state to any particular values.
>>> 	 */
>>> 	REG_WRITE(addr, 0x01, 0x0003);
>> This sort of enables auto-detection of speed.
>>
>>> isn't correct on ports that can either be CPU ports or external ports.
>> For external ports I had to enabled the PPU to allow the external PHYs
>> to negotiate.
> 
> The PPU should be re-enabled 10ms after the last MII access.
> 
> 
>> Also, on external PHYs ports 8 and 9, I write 0x0403 not 0x0003 (to
>> register 0x1, PCS Control Register).  Which also enables inband
>> auto-negotiation, but I'm not sure this is necessary.
> 
> Not sure whether it is.  Gary?
> 

I'm not sure either.  On my system, these ports are SERDES used to
cascade switches.  When we get that part working, we may learn if
these bits are important.

> 
>>> Forcing the link up on the CPU port helps somewhat, but things aren't
>>> 100% working yet.
>> On the CPU port I force link-up and force speed+duplex setting.  I only
>> got 100Mbit/s to the CPU port...
> 
> I suppose the cpu port speed should be made into a platform data
> config option in case there's only a 100 Mb/s link on a gigabit
> capable switch?

I agree.

-- 
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Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
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