From: Chris Rhodin <chris@notav8.com>
To: linux-mips@linux-mips.org
Subject: Enabling and Disabling Interrupts
Date: Tue, 07 Apr 2009 21:15:32 -0700 [thread overview]
Message-ID: <49DC24E4.7000704@notav8.com> (raw)
On cpus without the ei/di instructions, the macros local_irq_enable and
local_irq_disable use a read-modify-write of the status register to
change the IE bit. Doesn't this leave a window where an interrupting
context can change the status registers interrupt mask bits and have
that change reversed when the interrupted context resumes? Or possibly
this is covered by a policy I haven't figured out yet?
Thanks,
Chris Rhodin
reply other threads:[~2009-04-08 8:37 UTC|newest]
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