Re: [Qemu-devel] [PATCH] 64 bit I/O support v7

[Robert Reif <reif@earthlink.net>]

Robert Reif wrote:
>
> static void nvram_writel (void *opaque, target_phys_addr_t addr, 
> uint32_t value)
> {
>    m48t59_t *NVRAM = opaque;
>
>    m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
>    m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
>    m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
>    m48t59_write(NVRAM, addr + 3, value & 0xff);
> }
>
static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, 
uint32_t val)
{
#ifdef TARGET_WORDS_BIGENDIAN
    cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
    cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
    cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
    cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
#else
    cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
    cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
    cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
    cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
#endif
}

Should a new intermediate bus layer also do byte swapping?