[Qemu-devel] [PATCH] x86: Add support for resume flag

[Qemu-devel] [PATCH] x86: Add support for resume flag

[Jan Kiszka]

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Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---

 target-i386/cpu.h       |    9 ++++++---
 target-i386/helper.h    |    1 +
 target-i386/op_helper.c |    5 +++++
 target-i386/translate.c |    6 +++++-
 4 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index c6bca94..c892d82 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -145,11 +145,12 @@
 #define HF_IOPL_SHIFT       12 /* must be same as eflags */
 #define HF_LMA_SHIFT        14 /* only used on x86_64: long mode active */
 #define HF_CS64_SHIFT       15 /* only used on x86_64: 64 bit code segment  */
-#define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
+#define HF_RF_SHIFT         16 /* must be same as eflags */
 #define HF_VM_SHIFT         17 /* must be same as eflags */
 #define HF_SMM_SHIFT        19 /* CPU in SMM mode */
 #define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
 #define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
+#define HF_OSFXSR_SHIFT     22 /* CR4.OSFXSR */
 
 #define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
 #define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
@@ -165,11 +166,12 @@
 #define HF_IOPL_MASK         (3 << HF_IOPL_SHIFT)
 #define HF_LMA_MASK          (1 << HF_LMA_SHIFT)
 #define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
-#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
+#define HF_RF_MASK           (1 << HF_RF_SHIFT)
 #define HF_VM_MASK           (1 << HF_VM_SHIFT)
 #define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
 #define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
 #define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
+#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
 
 /* hflags2 */
 
@@ -880,7 +882,8 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 {
     *cs_base = env->segs[R_CS].base;
     *pc = *cs_base + env->eip;
-    *flags = env->hflags | (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
+    *flags = env->hflags |
+        (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK));
 }
 
 #endif /* CPU_I386_H */
diff --git a/target-i386/helper.h b/target-i386/helper.h
index 0c36783..68d57b1 100644
--- a/target-i386/helper.h
+++ b/target-i386/helper.h
@@ -62,6 +62,7 @@ DEF_HELPER_1(hlt, void, int)
 DEF_HELPER_1(monitor, void, tl)
 DEF_HELPER_1(mwait, void, int)
 DEF_HELPER_0(debug, void)
+DEF_HELPER_0(reset_rf, void)
 DEF_HELPER_2(raise_interrupt, void, int, int)
 DEF_HELPER_1(raise_exception, void, int)
 DEF_HELPER_0(cli, void)
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index f4cea08..bd1769c 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -4688,6 +4688,11 @@ void helper_debug(void)
     cpu_loop_exit();
 }
 
+void helper_reset_rf(void)
+{
+    env->eflags &= ~RF_MASK;
+}
+
 void helper_raise_interrupt(int intno, int next_eip_addend)
 {
     raise_interrupt(intno, 1, 0, next_eip_addend);
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8df3ea4..6582aad 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2705,6 +2705,9 @@ static void gen_eob(DisasContext *s)
     if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
         gen_helper_reset_inhibit_irq();
     }
+    if (s->tb->flags & HF_RF_MASK) {
+        gen_helper_reset_rf();
+    }
     if (s->singlestep_enabled) {
         gen_helper_debug();
     } else if (s->tf) {
@@ -7688,7 +7691,8 @@ static inline void gen_intermediate_code_internal(CPUState *env,
     for(;;) {
         if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
             TAILQ_FOREACH(bp, &env->breakpoints, entry) {
-                if (bp->pc == pc_ptr) {
+                if (bp->pc == pc_ptr &&
+                    !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
                     gen_debug(dc, pc_ptr - dc->cs_base);
                     break;
                 }


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