* Feasibility study: Linux on core 0, using other cores as worker cores. Octeon II
@ 2009-05-19 11:58 linux kernel
2009-05-19 16:16 ` Maciej W. Rozycki
2009-05-19 16:43 ` David Daney
0 siblings, 2 replies; 3+ messages in thread
From: linux kernel @ 2009-05-19 11:58 UTC (permalink / raw)
To: linux-kernel
Hi,
This might seem as an unusal feasibility question, but I would like to
discuss this here at LKML to hear you views on this matter.
The idea would be to build a IBM cell blade lookalike architecture,
using full blown linux on core 0, using the other cores as worker
threads.
Possible target CPUs are Octeon II with 32 cores or more.
The main goal for this would be to reduce interrupt latency for worker
cores, having them run possibly bare-bone with an IPC method between
core 0 and worker cores. probably DMA and HW IRQs.
Is there an existing system design in the kernel already that I can
expand/use ? Perhaps expanding/porting the cell blade IPC method.
What would you guys think would be the most efficient approach(and
perhaps would be acceptable to the LK maintainers for merging at a
later stage :) ) ?
Best Regards,
David
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Feasibility study: Linux on core 0, using other cores as worker cores. Octeon II
2009-05-19 11:58 Feasibility study: Linux on core 0, using other cores as worker cores. Octeon II linux kernel
@ 2009-05-19 16:16 ` Maciej W. Rozycki
2009-05-19 16:43 ` David Daney
1 sibling, 0 replies; 3+ messages in thread
From: Maciej W. Rozycki @ 2009-05-19 16:16 UTC (permalink / raw)
To: linux kernel; +Cc: linux-kernel, linux-mips
On Tue, 19 May 2009, linux kernel wrote:
> This might seem as an unusal feasibility question, but I would like to
> discuss this here at LKML to hear you views on this matter.
> The idea would be to build a IBM cell blade lookalike architecture,
> using full blown linux on core 0, using the other cores as worker
> threads.
> Possible target CPUs are Octeon II with 32 cores or more.
>
> The main goal for this would be to reduce interrupt latency for worker
> cores, having them run possibly bare-bone with an IPC method between
> core 0 and worker cores. probably DMA and HW IRQs.
>
> Is there an existing system design in the kernel already that I can
> expand/use ? Perhaps expanding/porting the cell blade IPC method.
> What would you guys think would be the most efficient approach(and
> perhaps would be acceptable to the LK maintainers for merging at a
> later stage :) ) ?
I'm not sure if there is a ready to use implementation available
anywhere, but what you've described is one of the proposed use models for
the MIPS 34K core. Of course the method of communication would differ.
You may want to search the Internet to see if you can find anything
relevant. Since the Octeon is a MIPS architecture implementation too I've
cc-ed the linux-mips list, where you might be able to get additional
responses; also about the 34K.
Maciej
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Feasibility study: Linux on core 0, using other cores as worker cores. Octeon II
2009-05-19 11:58 Feasibility study: Linux on core 0, using other cores as worker cores. Octeon II linux kernel
2009-05-19 16:16 ` Maciej W. Rozycki
@ 2009-05-19 16:43 ` David Daney
1 sibling, 0 replies; 3+ messages in thread
From: David Daney @ 2009-05-19 16:43 UTC (permalink / raw)
To: linux kernel; +Cc: linux-kernel, linux-mips
linux kernel wrote:
> Hi,
>
> This might seem as an unusal feasibility question, but I would like to
> discuss this here at LKML to hear you views on this matter.
> The idea would be to build a IBM cell blade lookalike architecture,
> using full blown linux on core 0, using the other cores as worker
> threads.
> Possible target CPUs are Octeon II with 32 cores or more.
>
> The main goal for this would be to reduce interrupt latency for worker
> cores, having them run possibly bare-bone with an IPC method between
> core 0 and worker cores. probably DMA and HW IRQs.
>
As you may be aware, this is a common use case for current users of
Octeon SOCs.
> Is there an existing system design in the kernel already that I can
> expand/use ? Perhaps expanding/porting the cell blade IPC method.
> What would you guys think would be the most efficient approach(and
> perhaps would be acceptable to the LK maintainers for merging at a
> later stage :) ) ?
Current Octeon applications, architected as you indicate, typically use
the SOC's work queue hardware for IPC, but this is via custom drivers,
not any existing kernel framework.
Since one of my main job functions is kernel development for the Octeon
family, I would certainly be interested in any work done in this area.
David Daney
^ permalink raw reply [flat|nested] 3+ messages in thread
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2009-05-19 11:58 Feasibility study: Linux on core 0, using other cores as worker cores. Octeon II linux kernel
2009-05-19 16:16 ` Maciej W. Rozycki
2009-05-19 16:43 ` David Daney
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