[U-Boot] [PATCH] change cpu.c under cpu/arm_cortexa8 dir to common code.

[U-Boot] [PATCH] change cpu.c under cpu/arm_cortexa8 dir to common code.

[Kim, Heung Jun]

The cpu.c under cpu/arm_cortexa8 has a dependency of omap3.
The part of cache in cpu.c is moved in the omap3/board.c,
because the functions about controlling cache seems to be different with a lot
of processors.

Signed-off-by: root <root@riverbuntu.(none)>
---
 cpu/arm_cortexa8/cpu.c                 |   55 +------------------------
 cpu/arm_cortexa8/omap3/board.c         |   68 ++++++++++++++++++++++++++++++++
 include/asm-arm/arch-omap3/sys_proto.h |    3 +
 3 files changed, 74 insertions(+), 52 deletions(-)

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 3e1780b..046a89e 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -97,64 +97,15 @@ int cleanup_before_linux(void)

 void l2cache_enable()
 {
-	unsigned long i;
-	volatile unsigned int j;
-
-	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() >= CPU_3XX_ES20) {
-		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
-		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
-		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-	} else {
-		/* Save r0, r12 and restore them after usage */
-		__asm__ __volatile__("mov %0, r12":"=r"(j));
-		__asm__ __volatile__("mov %0, r0":"=r"(i));
-
-		/*
-		 * GP Device ROM code API usage here
-		 * r12 = AUXCR Write function and r0 value
-		 */
-		__asm__ __volatile__("mov r12, #0x3");
-		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
-		__asm__ __volatile__("orr r0, r0, #0x2");
-		/* SMI instruction to call ROM Code API */
-		__asm__ __volatile__(".word 0xE1600070");
-		__asm__ __volatile__("mov r0, %0":"=r"(i));
-		__asm__ __volatile__("mov r12, %0":"=r"(j));
-	}
-
+	board_l2cache_enable();
 }

 void l2cache_disable()
 {
-	unsigned long i;
-	volatile unsigned int j;
-
-	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() >= CPU_3XX_ES20) {
-		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
-		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
-		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-	} else {
-		/* Save r0, r12 and restore them after usage */
-		__asm__ __volatile__("mov %0, r12":"=r"(j));
-		__asm__ __volatile__("mov %0, r0":"=r"(i));
-
-		/*
-		 * GP Device ROM code API usage here
-		 * r12 = AUXCR Write function and r0 value
-		 */
-		__asm__ __volatile__("mov r12, #0x3");
-		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
-		__asm__ __volatile__("bic r0, r0, #0x2");
-		/* SMI instruction to call ROM Code API */
-		__asm__ __volatile__(".word 0xE1600070");
-		__asm__ __volatile__("mov r0, %0":"=r"(i));
-		__asm__ __volatile__("mov r12, %0":"=r"(j));
-	}
+	board_l2cache_disable();
 }

 static void cache_flush(void)
 {
-	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+	board_cache_flush();
 }
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 51d5cf6..a594fc9 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -52,6 +52,74 @@ static inline void delay(unsigned long loops)
 }

 /******************************************************************************
+ * Routine: board_l2cache_enable() / disable() / flush()
+ * Description: cache enable / disable / flush
+ *****************************************************************************/
+void board_l2cache_enable()
+{
+	unsigned long i;
+	volatile unsigned int j;
+
+	/* ES2 onwards we can disable/enable L2 ourselves */
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
+		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
+		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+	} else {
+		/* Save r0, r12 and restore them after usage */
+		__asm__ __volatile__("mov %0, r12":"=r"(j));
+		__asm__ __volatile__("mov %0, r0":"=r"(i));
+
+		/*
+		 * GP Device ROM code API usage here
+		 * r12 = AUXCR Write function and r0 value
+		 */
+		__asm__ __volatile__("mov r12, #0x3");
+		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+		__asm__ __volatile__("orr r0, r0, #0x2");
+		/* SMI instruction to call ROM Code API */
+		__asm__ __volatile__(".word 0xE1600070");
+		__asm__ __volatile__("mov r0, %0":"=r"(i));
+		__asm__ __volatile__("mov r12, %0":"=r"(j));
+	}
+
+}
+
+void board_l2cache_disable()
+{
+	unsigned long i;
+	volatile unsigned int j;
+
+	/* ES2 onwards we can disable/enable L2 ourselves */
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
+		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r"(i));
+		__asm__ __volatile__("bic %0, %0, #0x2" : "=r"(i));
+		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : "=r"(i));
+	} else {
+		/* Save r0, r12 and restore them after usage */
+		__asm__ __volatile__("mov %0, r12" : "=r"(j));
+		__asm__ __volatile__("mov %0, r0" : "=r"(i));
+
+		/*
+		 * GP Device ROM code API usage here
+		 * r12 = AUXCR Write function and r0 value
+		 */
+		__asm__ __volatile__("mov r12, #0x3");
+		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+		__asm__ __volatile__("bic r0, r0, #0x2");
+		/* SMI instruction to call ROM Code API */
+		__asm__ __volatile__(".word 0xE1600070");
+		__asm__ __volatile__("mov r0, %0" : "=r"(i));
+		__asm__ __volatile__("mov r12, %0" : "=r"(j));
+	}
+}
+
+void board_cache_flush(void)
+{
+	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+}
+
+/******************************************************************************
  * Routine: secure_unlock
  * Description: Setup security registers for access
  *              (GP Device only)
diff --git a/include/asm-arm/arch-omap3/sys_proto.h
b/include/asm-arm/arch-omap3/sys_proto.h
index 7361d08..06a0d8a 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -63,5 +63,8 @@ void make_cs1_contiguous(void);
 void omap_nand_switch_ecc(int);
 void power_init_r(void);
 void dieid_num_r(void);
+void board_l2cache_enable();
+void board_l2cache_disable();
+void board_cache_flush();

 #endif
-- 
1.5.6.3

[U-Boot] [PATCH] change cpu.c under cpu/arm_cortexa8 dir to common code.

[Kim, Heung Jun]

Sorry about wrong Signed-off-by.

Signed-off-by: riverful.kim <riverful.kim@samsung.com>

Regards,
Kim, HeungJun


2009/5/27 Kim, Heung Jun <riverful@gmail.com>:
> The cpu.c under cpu/arm_cortexa8 has a dependency of omap3.
> The part of cache in cpu.c is moved in the omap3/board.c,
> because the functions about controlling cache seems to be different with a lot
> of processors.
>
> Signed-off-by: root <root@riverbuntu.(none)>
> ---
> ?cpu/arm_cortexa8/cpu.c ? ? ? ? ? ? ? ? | ? 55 +------------------------
> ?cpu/arm_cortexa8/omap3/board.c ? ? ? ? | ? 68 ++++++++++++++++++++++++++++++++
> ?include/asm-arm/arch-omap3/sys_proto.h | ? ?3 +
> ?3 files changed, 74 insertions(+), 52 deletions(-)
>
> diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
> index 3e1780b..046a89e 100644
> --- a/cpu/arm_cortexa8/cpu.c
> +++ b/cpu/arm_cortexa8/cpu.c
> @@ -97,64 +97,15 @@ int cleanup_before_linux(void)
>
> ?void l2cache_enable()
> ?{
> - ? ? ? unsigned long i;
> - ? ? ? volatile unsigned int j;
> -
> - ? ? ? /* ES2 onwards we can disable/enable L2 ourselves */
> - ? ? ? if (get_cpu_rev() >= CPU_3XX_ES20) {
> - ? ? ? ? ? ? ? __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> - ? ? ? ? ? ? ? __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
> - ? ? ? ? ? ? ? __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> - ? ? ? } else {
> - ? ? ? ? ? ? ? /* Save r0, r12 and restore them after usage */
> - ? ? ? ? ? ? ? __asm__ __volatile__("mov %0, r12":"=r"(j));
> - ? ? ? ? ? ? ? __asm__ __volatile__("mov %0, r0":"=r"(i));
> -
> - ? ? ? ? ? ? ? /*
> - ? ? ? ? ? ? ? ?* GP Device ROM code API usage here
> - ? ? ? ? ? ? ? ?* r12 = AUXCR Write function and r0 value
> - ? ? ? ? ? ? ? ?*/
> - ? ? ? ? ? ? ? __asm__ __volatile__("mov r12, #0x3");
> - ? ? ? ? ? ? ? __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> - ? ? ? ? ? ? ? __asm__ __volatile__("orr r0, r0, #0x2");
> - ? ? ? ? ? ? ? /* SMI instruction to call ROM Code API */
> - ? ? ? ? ? ? ? __asm__ __volatile__(".word 0xE1600070");
> - ? ? ? ? ? ? ? __asm__ __volatile__("mov r0, %0":"=r"(i));
> - ? ? ? ? ? ? ? __asm__ __volatile__("mov r12, %0":"=r"(j));
> - ? ? ? }
> -
> + ? ? ? board_l2cache_enable();
> ?}
>
> ?void l2cache_disable()
> ?{
> - ? ? ? unsigned long i;
> - ? ? ? volatile unsigned int j;
> -
> - ? ? ? /* ES2 onwards we can disable/enable L2 ourselves */
> - ? ? ? if (get_cpu_rev() >= CPU_3XX_ES20) {
> - ? ? ? ? ? ? ? __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> - ? ? ? ? ? ? ? __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
> - ? ? ? ? ? ? ? __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> - ? ? ? } else {
> - ? ? ? ? ? ? ? /* Save r0, r12 and restore them after usage */
> - ? ? ? ? ? ? ? __asm__ __volatile__("mov %0, r12":"=r"(j));
> - ? ? ? ? ? ? ? __asm__ __volatile__("mov %0, r0":"=r"(i));
> -
> - ? ? ? ? ? ? ? /*
> - ? ? ? ? ? ? ? ?* GP Device ROM code API usage here
> - ? ? ? ? ? ? ? ?* r12 = AUXCR Write function and r0 value
> - ? ? ? ? ? ? ? ?*/
> - ? ? ? ? ? ? ? __asm__ __volatile__("mov r12, #0x3");
> - ? ? ? ? ? ? ? __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> - ? ? ? ? ? ? ? __asm__ __volatile__("bic r0, r0, #0x2");
> - ? ? ? ? ? ? ? /* SMI instruction to call ROM Code API */
> - ? ? ? ? ? ? ? __asm__ __volatile__(".word 0xE1600070");
> - ? ? ? ? ? ? ? __asm__ __volatile__("mov r0, %0":"=r"(i));
> - ? ? ? ? ? ? ? __asm__ __volatile__("mov r12, %0":"=r"(j));
> - ? ? ? }
> + ? ? ? board_l2cache_disable();
> ?}
>
> ?static void cache_flush(void)
> ?{
> - ? ? ? asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
> + ? ? ? board_cache_flush();
> ?}
> diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
> index 51d5cf6..a594fc9 100644
> --- a/cpu/arm_cortexa8/omap3/board.c
> +++ b/cpu/arm_cortexa8/omap3/board.c
> @@ -52,6 +52,74 @@ static inline void delay(unsigned long loops)
> ?}
>
> ?/******************************************************************************
> + * Routine: board_l2cache_enable() / disable() / flush()
> + * Description: cache enable / disable / flush
> + *****************************************************************************/
> +void board_l2cache_enable()
> +{
> + ? ? ? unsigned long i;
> + ? ? ? volatile unsigned int j;
> +
> + ? ? ? /* ES2 onwards we can disable/enable L2 ourselves */
> + ? ? ? if (get_cpu_rev() >= CPU_3XX_ES20) {
> + ? ? ? ? ? ? ? __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> + ? ? ? ? ? ? ? __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
> + ? ? ? ? ? ? ? __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> + ? ? ? } else {
> + ? ? ? ? ? ? ? /* Save r0, r12 and restore them after usage */
> + ? ? ? ? ? ? ? __asm__ __volatile__("mov %0, r12":"=r"(j));
> + ? ? ? ? ? ? ? __asm__ __volatile__("mov %0, r0":"=r"(i));
> +
> + ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ?* GP Device ROM code API usage here
> + ? ? ? ? ? ? ? ?* r12 = AUXCR Write function and r0 value
> + ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? __asm__ __volatile__("mov r12, #0x3");
> + ? ? ? ? ? ? ? __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> + ? ? ? ? ? ? ? __asm__ __volatile__("orr r0, r0, #0x2");
> + ? ? ? ? ? ? ? /* SMI instruction to call ROM Code API */
> + ? ? ? ? ? ? ? __asm__ __volatile__(".word 0xE1600070");
> + ? ? ? ? ? ? ? __asm__ __volatile__("mov r0, %0":"=r"(i));
> + ? ? ? ? ? ? ? __asm__ __volatile__("mov r12, %0":"=r"(j));
> + ? ? ? }
> +
> +}
> +
> +void board_l2cache_disable()
> +{
> + ? ? ? unsigned long i;
> + ? ? ? volatile unsigned int j;
> +
> + ? ? ? /* ES2 onwards we can disable/enable L2 ourselves */
> + ? ? ? if (get_cpu_rev() >= CPU_3XX_ES20) {
> + ? ? ? ? ? ? ? __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r"(i));
> + ? ? ? ? ? ? ? __asm__ __volatile__("bic %0, %0, #0x2" : "=r"(i));
> + ? ? ? ? ? ? ? __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : "=r"(i));
> + ? ? ? } else {
> + ? ? ? ? ? ? ? /* Save r0, r12 and restore them after usage */
> + ? ? ? ? ? ? ? __asm__ __volatile__("mov %0, r12" : "=r"(j));
> + ? ? ? ? ? ? ? __asm__ __volatile__("mov %0, r0" : "=r"(i));
> +
> + ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ?* GP Device ROM code API usage here
> + ? ? ? ? ? ? ? ?* r12 = AUXCR Write function and r0 value
> + ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? __asm__ __volatile__("mov r12, #0x3");
> + ? ? ? ? ? ? ? __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> + ? ? ? ? ? ? ? __asm__ __volatile__("bic r0, r0, #0x2");
> + ? ? ? ? ? ? ? /* SMI instruction to call ROM Code API */
> + ? ? ? ? ? ? ? __asm__ __volatile__(".word 0xE1600070");
> + ? ? ? ? ? ? ? __asm__ __volatile__("mov r0, %0" : "=r"(i));
> + ? ? ? ? ? ? ? __asm__ __volatile__("mov r12, %0" : "=r"(j));
> + ? ? ? }
> +}
> +
> +void board_cache_flush(void)
> +{
> + ? ? ? asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
> +}
> +
> +/******************************************************************************
> ?* Routine: secure_unlock
> ?* Description: Setup security registers for access
> ?* ? ? ? ? ? ? ?(GP Device only)
> diff --git a/include/asm-arm/arch-omap3/sys_proto.h
> b/include/asm-arm/arch-omap3/sys_proto.h
> index 7361d08..06a0d8a 100644
> --- a/include/asm-arm/arch-omap3/sys_proto.h
> +++ b/include/asm-arm/arch-omap3/sys_proto.h
> @@ -63,5 +63,8 @@ void make_cs1_contiguous(void);
> ?void omap_nand_switch_ecc(int);
> ?void power_init_r(void);
> ?void dieid_num_r(void);
> +void board_l2cache_enable();
> +void board_l2cache_disable();
> +void board_cache_flush();
>
> ?#endif
> --
> 1.5.6.3
>

[U-Boot] [PATCH] change cpu.c under cpu/arm_cortexa8 dir to common code.

[Dirk Behme]

Kim, Heung Jun wrote:
> The cpu.c under cpu/arm_cortexa8 has a dependency of omap3.
> The part of cache in cpu.c is moved in the omap3/board.c,
> because the functions about controlling cache seems to be different with a lot
> of processors.

I guess you noticed this while adding an other Cortex A8 device?

Anyway, yes, from functionality point of view I agree this patch. 
OMAP3 was the first Cortex A8 device. So it was more or less expected 
that while adding additional ones we have to re-arrange some stuff. 
Being the first adding new stuff, you can't really know what might be 
generic and what not ;)

The only thing I'd like to discuss is how to name the functions. 
Naming the functions board_*() doesn't seem to fit. Cache 
functionality isn't really board related. Regarding L2Cache, this is 
CPU/SoC related. So maybe omap3_l2cache_*()?

Regarding cache_flush()/board_cache_flush() below maybe 
Jean-Christophe can help if we have already something generic for this 
somewhere? If not, we should use something like omap3_cache_flush().

Best regards

Dirk

> Signed-off-by: root <root@riverbuntu.(none)>
> ---
>  cpu/arm_cortexa8/cpu.c                 |   55 +------------------------
>  cpu/arm_cortexa8/omap3/board.c         |   68 ++++++++++++++++++++++++++++++++
>  include/asm-arm/arch-omap3/sys_proto.h |    3 +
>  3 files changed, 74 insertions(+), 52 deletions(-)
> 
> diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
> index 3e1780b..046a89e 100644
> --- a/cpu/arm_cortexa8/cpu.c
> +++ b/cpu/arm_cortexa8/cpu.c
> @@ -97,64 +97,15 @@ int cleanup_before_linux(void)
> 
>  void l2cache_enable()
>  {
> -	unsigned long i;
> -	volatile unsigned int j;
> -
> -	/* ES2 onwards we can disable/enable L2 ourselves */
> -	if (get_cpu_rev() >= CPU_3XX_ES20) {
> -		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> -		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
> -		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> -	} else {
> -		/* Save r0, r12 and restore them after usage */
> -		__asm__ __volatile__("mov %0, r12":"=r"(j));
> -		__asm__ __volatile__("mov %0, r0":"=r"(i));
> -
> -		/*
> -		 * GP Device ROM code API usage here
> -		 * r12 = AUXCR Write function and r0 value
> -		 */
> -		__asm__ __volatile__("mov r12, #0x3");
> -		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> -		__asm__ __volatile__("orr r0, r0, #0x2");
> -		/* SMI instruction to call ROM Code API */
> -		__asm__ __volatile__(".word 0xE1600070");
> -		__asm__ __volatile__("mov r0, %0":"=r"(i));
> -		__asm__ __volatile__("mov r12, %0":"=r"(j));
> -	}
> -
> +	board_l2cache_enable();
>  }
> 
>  void l2cache_disable()
>  {
> -	unsigned long i;
> -	volatile unsigned int j;
> -
> -	/* ES2 onwards we can disable/enable L2 ourselves */
> -	if (get_cpu_rev() >= CPU_3XX_ES20) {
> -		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> -		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
> -		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> -	} else {
> -		/* Save r0, r12 and restore them after usage */
> -		__asm__ __volatile__("mov %0, r12":"=r"(j));
> -		__asm__ __volatile__("mov %0, r0":"=r"(i));
> -
> -		/*
> -		 * GP Device ROM code API usage here
> -		 * r12 = AUXCR Write function and r0 value
> -		 */
> -		__asm__ __volatile__("mov r12, #0x3");
> -		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> -		__asm__ __volatile__("bic r0, r0, #0x2");
> -		/* SMI instruction to call ROM Code API */
> -		__asm__ __volatile__(".word 0xE1600070");
> -		__asm__ __volatile__("mov r0, %0":"=r"(i));
> -		__asm__ __volatile__("mov r12, %0":"=r"(j));
> -	}
> +	board_l2cache_disable();
>  }
> 
>  static void cache_flush(void)
>  {
> -	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
> +	board_cache_flush();
>  }
> diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
> index 51d5cf6..a594fc9 100644
> --- a/cpu/arm_cortexa8/omap3/board.c
> +++ b/cpu/arm_cortexa8/omap3/board.c
> @@ -52,6 +52,74 @@ static inline void delay(unsigned long loops)
>  }
> 
>  /******************************************************************************
> + * Routine: board_l2cache_enable() / disable() / flush()
> + * Description: cache enable / disable / flush
> + *****************************************************************************/
> +void board_l2cache_enable()
> +{
> +	unsigned long i;
> +	volatile unsigned int j;
> +
> +	/* ES2 onwards we can disable/enable L2 ourselves */
> +	if (get_cpu_rev() >= CPU_3XX_ES20) {
> +		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
> +		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
> +		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
> +	} else {
> +		/* Save r0, r12 and restore them after usage */
> +		__asm__ __volatile__("mov %0, r12":"=r"(j));
> +		__asm__ __volatile__("mov %0, r0":"=r"(i));
> +
> +		/*
> +		 * GP Device ROM code API usage here
> +		 * r12 = AUXCR Write function and r0 value
> +		 */
> +		__asm__ __volatile__("mov r12, #0x3");
> +		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> +		__asm__ __volatile__("orr r0, r0, #0x2");
> +		/* SMI instruction to call ROM Code API */
> +		__asm__ __volatile__(".word 0xE1600070");
> +		__asm__ __volatile__("mov r0, %0":"=r"(i));
> +		__asm__ __volatile__("mov r12, %0":"=r"(j));
> +	}
> +
> +}
> +
> +void board_l2cache_disable()
> +{
> +	unsigned long i;
> +	volatile unsigned int j;
> +
> +	/* ES2 onwards we can disable/enable L2 ourselves */
> +	if (get_cpu_rev() >= CPU_3XX_ES20) {
> +		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1" : "=r"(i));
> +		__asm__ __volatile__("bic %0, %0, #0x2" : "=r"(i));
> +		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1" : "=r"(i));
> +	} else {
> +		/* Save r0, r12 and restore them after usage */
> +		__asm__ __volatile__("mov %0, r12" : "=r"(j));
> +		__asm__ __volatile__("mov %0, r0" : "=r"(i));
> +
> +		/*
> +		 * GP Device ROM code API usage here
> +		 * r12 = AUXCR Write function and r0 value
> +		 */
> +		__asm__ __volatile__("mov r12, #0x3");
> +		__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
> +		__asm__ __volatile__("bic r0, r0, #0x2");
> +		/* SMI instruction to call ROM Code API */
> +		__asm__ __volatile__(".word 0xE1600070");
> +		__asm__ __volatile__("mov r0, %0" : "=r"(i));
> +		__asm__ __volatile__("mov r12, %0" : "=r"(j));
> +	}
> +}
> +
> +void board_cache_flush(void)
> +{
> +	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
> +}
> +
> +/******************************************************************************
>   * Routine: secure_unlock
>   * Description: Setup security registers for access
>   *              (GP Device only)
> diff --git a/include/asm-arm/arch-omap3/sys_proto.h
> b/include/asm-arm/arch-omap3/sys_proto.h
> index 7361d08..06a0d8a 100644
> --- a/include/asm-arm/arch-omap3/sys_proto.h
> +++ b/include/asm-arm/arch-omap3/sys_proto.h
> @@ -63,5 +63,8 @@ void make_cs1_contiguous(void);
>  void omap_nand_switch_ecc(int);
>  void power_init_r(void);
>  void dieid_num_r(void);
> +void board_l2cache_enable();
> +void board_l2cache_disable();
> +void board_cache_flush();
> 
>  #endif

[U-Boot] [PATCH] change cpu.c under cpu/arm_cortexa8 dir to common code.

[Jean-Christophe PLAGNIOL-VILLARD]

> The only thing I'd like to discuss is how to name the functions. Naming 
> the functions board_*() doesn't seem to fit. Cache functionality isn't 
> really board related. Regarding L2Cache, this is CPU/SoC related. So 
> maybe omap3_l2cache_*()?
actually I'd like to have a better cache management API and you point the
board_ does not fit here as the code is soc or arch specific
>
> Regarding cache_flush()/board_cache_flush() below maybe Jean-Christophe 
> can help if we have already something generic for this somewhere? If not, 
> we should use something like omap3_cache_flush().
as we will support only one arch simultany I'll prefer to not specify it's
name at all.

you will ask why? The reason is that I do want have a common cache management
and a common cleanup before linux

so I'll propose l2_cache_flush as done for the Marvell orion

for non-l2 cache I prefer to manage it via armvXX as they will be common

Best Regards,
J.

[U-Boot] [PATCH] change cpu.c under cpu/arm_cortexa8 dir to common code.

[Kim, Heung Jun]

First of all, thanks for reading this to Dirk, Jean-Christophe.

>> Anyway, yes, from functionality point of view I agree this patch. OMAP3 was the first Cortex A8 device. So it was more or less expected that while adding additional ones we have to re-arrange some stuff. Being the first adding new stuff, you can't really know what might be generic and what not ;)
Dirk? Definitely, Yes :)
Actually, we wanna make new codes for Cortex A8 CPU - the name of s5pc100,
and send the new patch of it.
But, while making the new specific code about s5pc100,
we found cpu/arm_cortexa8/cpu.c has the dependent function l2cache_enable() /
l2cache_diable() / cache_flush() on omap3 i guess.
Although s5pc100 specific code dosen't use this dependent code,
compile error occured cause of get_device_type().

So, we had to send patch file about removing dependency cpu core first.

After this issue was resolved, I'll plan to send the s5pc100 core patch.


2009/5/28 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>:
>> The only thing I'd like to discuss is how to name the functions. Naming
>> the functions board_*() doesn't seem to fit. Cache functionality isn't
>> really board related. Regarding L2Cache, this is CPU/SoC related. So
>> maybe omap3_l2cache_*()?
> actually I'd like to have a better cache management API and you point the
> board_ does not fit here as the code is soc or arch specific
>>
>> Regarding cache_flush()/board_cache_flush() below maybe Jean-Christophe
>> can help if we have already something generic for this somewhere? If not,
>> we should use something like omap3_cache_flush().
> as we will support only one arch simultany I'll prefer to not specify it's
> name at all.
>
> you will ask why? The reason is that I do want have a common cache management
> and a common cleanup before linux
>
> so I'll propose l2_cache_flush as done for the Marvell orion
>
> for non-l2 cache I prefer to manage it via armvXX as they will be common
Jean? Ok. I agree with that. So, what name do we use?
For example, can we make the function name of l2_cache_enable() into
any other files
under the directory of cpu/arm_cortex/sp5c100/ ??

Our goal is making the s5pc100 core patch, and reflecting(?) it on the
u-boot mainline.
If the exact common function name is decided, we are able to do the
new patch works.
I'd like to get the name of cache common funcion, plz :)


Best Regards,
HeungJun Kim(riverful).