From: Michal Simek <michal.simek@petalogix.com>
To: Paul Mundt <lethal@linux-sh.org>,
Michal Simek <michal.simek@petalogix.com>,
Arnd Bergmann <arnd@arndb.de>,
Linux Kernel list <linux-kernel@vger.kernel.org>,
LTP <ltp-list@lists.sourceforge.net>,
John Williams <john.williams@petalogix.com>,
Ingo Molnar <mingo@elte.hu>,
Andrew Morton <akpm@linux-foundation.org>,
Grant Likely <grant.likely@secretlab.ca>,
subrata@linux.vnet.ibm.com
Subject: Re: [LTP] mmap syscall problem
Date: Mon, 06 Jul 2009 14:54:11 +0200 [thread overview]
Message-ID: <4A51F3F3.6040501@petalogix.com> (raw)
In-Reply-To: <20090706121455.GA16908@linux-sh.org>
Paul Mundt wrote:
> On Mon, Jul 06, 2009 at 02:07:06PM +0200, Michal Simek wrote:
>
>> Arnd Bergmann wrote:
>>
>>> On Monday 06 July 2009, Michal Simek wrote:
>>>
>>>
>>>>> Does this happen on microblaze-mmu or microblaze-nommu, or both?
>>>>> The mmap code for the two is very different.
>>>>>
>>>>>
>>>>>
>>>> For MMU code.
>>>>
>>>>
>>> Could this be a cache-aliasing problem? If your cache is 'virtually-indexed'
>>> (most architectures are 'physically-indexed'), the kernel may have written
>>> into different parts of the D-cache than what the user space is reading
>>> from. If you have a write-through cache, that can explain why you only
>>> see the stale data at the beginning of the page -- the cache controller
>>> is still busy writing back the data when you start reading it from
>>> DRAM through the cache alias.
>>>
>>>
>> I don't think so because we run that test on Microblaze without caches
>> and test failed too.
>> I think that this is sufficient test to tell that the problem is not
>> relate with caches.
>>
>>
> Not necessarily, even on platforms that manage aliases in hardware
> mappings that violate the aliasing constraints can still result in
> undefined behaviour, this really depends more on your cache controller
> and MMU than anything else. I notice that microblaze sets SHMLBA to
> PAGE_SIZE, you may want to see if this test still breaks after bumping it
> up to something like PAGE_SIZE * 4.
>
Yes, test still break - behavior is the same. I don't have accurate
information about MMU unit
but I will ask a question about. We are able to turn off cache
controller directly in HW.
> This is unfortunately one of the areas where what POSIX says is possible
> and what hardware can support are at odds (you can look through
> arch/sh/mm/mmap.c for a better idea).
>
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
PetaLogix - Linux Solutions for a Reconfigurable World
w: www.petalogix.com p: +61-7-30090663,+42-0-721842854 f: +61-7-30090663
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WARNING: multiple messages have this Message-ID (diff)
From: Michal Simek <michal.simek@petalogix.com>
To: Paul Mundt <lethal@linux-sh.org>,
Michal Simek <michal.simek@petalogix.com>,
Arnd Bergmann <arnd@arndb.de>,
Linux Kernel list <linux-kernel@vger.kernel.org>,
LTP <ltp-list@lists.sourceforge.net>,
John Williams <john.williams@petalogix.com>,
Ingo Molnar <mingo@elte.hu>,
Andrew Morton <akpm@linux-foundation.org>,
Grant Likely <grant.likely@secretlab.ca>,
subrata@linux.vnet.ibm.com
Subject: Re: mmap syscall problem
Date: Mon, 06 Jul 2009 14:54:11 +0200 [thread overview]
Message-ID: <4A51F3F3.6040501@petalogix.com> (raw)
In-Reply-To: <20090706121455.GA16908@linux-sh.org>
Paul Mundt wrote:
> On Mon, Jul 06, 2009 at 02:07:06PM +0200, Michal Simek wrote:
>
>> Arnd Bergmann wrote:
>>
>>> On Monday 06 July 2009, Michal Simek wrote:
>>>
>>>
>>>>> Does this happen on microblaze-mmu or microblaze-nommu, or both?
>>>>> The mmap code for the two is very different.
>>>>>
>>>>>
>>>>>
>>>> For MMU code.
>>>>
>>>>
>>> Could this be a cache-aliasing problem? If your cache is 'virtually-indexed'
>>> (most architectures are 'physically-indexed'), the kernel may have written
>>> into different parts of the D-cache than what the user space is reading
>>> from. If you have a write-through cache, that can explain why you only
>>> see the stale data at the beginning of the page -- the cache controller
>>> is still busy writing back the data when you start reading it from
>>> DRAM through the cache alias.
>>>
>>>
>> I don't think so because we run that test on Microblaze without caches
>> and test failed too.
>> I think that this is sufficient test to tell that the problem is not
>> relate with caches.
>>
>>
> Not necessarily, even on platforms that manage aliases in hardware
> mappings that violate the aliasing constraints can still result in
> undefined behaviour, this really depends more on your cache controller
> and MMU than anything else. I notice that microblaze sets SHMLBA to
> PAGE_SIZE, you may want to see if this test still breaks after bumping it
> up to something like PAGE_SIZE * 4.
>
Yes, test still break - behavior is the same. I don't have accurate
information about MMU unit
but I will ask a question about. We are able to turn off cache
controller directly in HW.
> This is unfortunately one of the areas where what POSIX says is possible
> and what hardware can support are at odds (you can look through
> arch/sh/mm/mmap.c for a better idea).
>
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
PetaLogix - Linux Solutions for a Reconfigurable World
w: www.petalogix.com p: +61-7-30090663,+42-0-721842854 f: +61-7-30090663
next prev parent reply other threads:[~2009-07-06 12:54 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-07-03 12:37 [LTP] mmap syscall problem Michal Simek
2009-07-03 12:37 ` Michal Simek
2009-07-03 15:02 ` [LTP] " Arnd Bergmann
2009-07-03 15:02 ` Arnd Bergmann
2009-07-06 6:32 ` [LTP] " Michal Simek
2009-07-06 6:32 ` Michal Simek
2009-07-06 8:05 ` [LTP] " Arnd Bergmann
2009-07-06 8:05 ` Arnd Bergmann
2009-07-06 12:07 ` [LTP] " Michal Simek
2009-07-06 12:07 ` Michal Simek
2009-07-06 12:14 ` [LTP] " Paul Mundt
2009-07-06 12:14 ` Paul Mundt
2009-07-06 12:54 ` Michal Simek [this message]
2009-07-06 12:54 ` Michal Simek
2009-07-06 14:16 ` [LTP] " Arnd Bergmann
2009-07-06 14:16 ` Arnd Bergmann
2009-07-06 14:43 ` [LTP] " Michal Simek
2009-07-06 14:43 ` Michal Simek
2009-07-06 15:05 ` [LTP] " Arnd Bergmann
2009-07-06 15:05 ` Arnd Bergmann
2009-07-06 15:19 ` [LTP] " Michal Simek
2009-07-06 15:19 ` Michal Simek
2009-07-07 0:44 ` [LTP] " Valdis.Kletnieks
2009-07-07 0:44 ` Valdis.Kletnieks
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