* [U-Boot] [PATCH RESEND 0/3] arm: Add support for MB86R01 'Jade' SoC @ 2009-07-08 14:02 Matthias Weisser 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 1/3] arm: Added " Matthias Weisser 0 siblings, 1 reply; 11+ messages in thread From: Matthias Weisser @ 2009-07-08 14:02 UTC (permalink / raw) To: u-boot This patchset adds support for the MB86R01 'Jade' SoC from Fujitsu. The second patch which adds the video driver needs this patch http://lists.denx.de/pipermail/u-boot/2009-July/055582.html which adds register offset definitions for the graphic controller. This time I ran checkpatch.pl from the linux kernel sources for all patches and hopefully ignored only things which are not critical for inclusion of my source into u-boot. Matthias Weisser ^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH RESEND 1/3] arm: Added support for MB86R01 'Jade' SoC 2009-07-08 14:02 [U-Boot] [PATCH RESEND 0/3] arm: Add support for MB86R01 'Jade' SoC Matthias Weisser @ 2009-07-08 14:02 ` Matthias Weisser 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in Jade SoC Matthias Weisser 2009-07-08 21:27 ` [U-Boot] [PATCH RESEND 1/3] arm: Added support for MB86R01 'Jade' SoC Jean-Christophe PLAGNIOL-VILLARD 0 siblings, 2 replies; 11+ messages in thread From: Matthias Weisser @ 2009-07-08 14:02 UTC (permalink / raw) To: u-boot This patch adds support for MB86R01 'Jade' SoC from Fujitsu Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de> --- cpu/arm926ejs/jade/Makefile | 47 +++++++++ cpu/arm926ejs/jade/timer.c | 126 ++++++++++++++++++++++++ include/asm-arm/arch-jade/hardware.h | 31 ++++++ include/asm-arm/arch-jade/jade.h | 177 ++++++++++++++++++++++++++++++++++ 4 files changed, 381 insertions(+), 0 deletions(-) create mode 100644 cpu/arm926ejs/jade/Makefile create mode 100644 cpu/arm926ejs/jade/timer.c create mode 100644 include/asm-arm/arch-jade/hardware.h create mode 100644 include/asm-arm/arch-jade/jade.h diff --git a/cpu/arm926ejs/jade/Makefile b/cpu/arm926ejs/jade/Makefile new file mode 100644 index 0000000..7da9f40 --- /dev/null +++ b/cpu/arm926ejs/jade/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o +SOBJS = + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/jade/timer.c b/cpu/arm926ejs/jade/timer.c new file mode 100644 index 0000000..2d262c8 --- /dev/null +++ b/cpu/arm926ejs/jade/timer.c @@ -0,0 +1,126 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * Matthias Weisser <matthias.weisser@graf-syteco.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <div64.h> + +#define TIMER_LOAD_VAL 0xffffffff +#define TIMER_BASE 0xfffe0000 + +#define READ_TIMER (*(volatile ulong *)(TIMER_BASE+4)) +#define TIMER_FREQ (CONFIG_JADE_IOCLK / 16) + +static ulong timestamp; +static ulong lastdec; + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, TIMER_FREQ); + + return tick; +} + +static inline unsigned long long usec_to_tick(unsigned long long usec) +{ + usec *= TIMER_FREQ; + do_div(usec, 1000000); + + return usec; +} + +/* nothing really to do with interrupts, just starts up a counter. */ +int timer_init(void) +{ + *(volatile ulong *)(TIMER_BASE + 0) = TIMER_LOAD_VAL; + *(volatile ulong *)(TIMER_BASE + 8) = 0x86; + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ +unsigned long long get_ticks(void) +{ + ulong now = READ_TIMER; + + if (now <= lastdec) /* normal mode (non roll) */ + /* move stamp forward with absolut diff ticks */ + timestamp += (lastdec - now); + else /* we have rollover of incrementer */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + lastdec = now; + return timestamp; +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER; /* capture current decrement value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked(void) +{ + return tick_to_time(get_ticks()); +} + +void udelay(unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = usec_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + return tbclk; +} diff --git a/include/asm-arm/arch-jade/hardware.h b/include/asm-arm/arch-jade/hardware.h new file mode 100644 index 0000000..a26bdca --- /dev/null +++ b/include/asm-arm/arch-jade/hardware.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 + * + * Author : Carsten Schneider, mycable GmbH + * <cs@mycable.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> +#include <asm/arch/jade.h> + +#endif diff --git a/include/asm-arm/arch-jade/jade.h b/include/asm-arm/arch-jade/jade.h new file mode 100644 index 0000000..c2b28a2 --- /dev/null +++ b/include/asm-arm/arch-jade/jade.h @@ -0,0 +1,177 @@ +/* + * (C) Copyright 2007 + * + * jade definitions + * + * Author : Carsten Schneider, mycable GmbH + * <cs@mycable.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef JADE_H +#define JADE_H + +typedef volatile unsigned int JREG; /* Hardware register */ + +/* + * Physical Address Defines + */ +#define JADE_GDC_PHYS_BASE 0xf1fc0000 +#define JADE_GDC_PHYS_DISP_BASE 0xf1fd0000 +#define JADE_CCNT_PHYS_BASE 0xfff42000 +#define JADE_CAN0_PHYS_BASE 0xfff54000 +#define JADE_CAN1_PHYS_BASE 0xfff55000 +#define JADE_I2C0_PHYS_BASE 0xfff56000 +#define JADE_I2C1_PHYS_BASE 0xfff57000 +#define JADE_EHCI_PHYS_BASE 0xfff80000 +#define JADE_OHCI_PHYS_BASE 0xfff81000 +#define JADE_IRC1_PHYS_BASE 0xfffb0000 +#define JADE_TIMER_PHYS_BASE 0xfffe0000 +#define JADE_UART0_PHYS_BASE 0xfffe1000 +#define JADE_UART1_PHYS_BASE 0xfffe2000 +#define JADE_IRCE_PHYS_BASE 0xfffe4000 +#define JADE_CRG_PHYS_BASE 0xfffe7000 +#define JADE_IRC0_PHYS_BASE 0xfffe8000 +#define JADE_GPIO_PHYS_BASE 0xfffe9000 + + +/* DRAMC_DRIC DRAM Controller Mode Register */ + +/* + * REGISTER ADDRESS DEFINITION FOR DRAMC PERIPHERAL + */ +#define JREGC_DRAMC_DRIC ((JREG *) 0xF3000000) +#define JREGC_DRAMC_DRIC1 ((JREG *) 0xF3000002) +#define JREGC_DRAMC_DRIC2 ((JREG *) 0xF3000004) +#define JREGC_DRAMC_DRCA ((JREG *) 0xF3000006) +#define JREGC_DRAMC_DRCM ((JREG *) 0xF3000008) +#define JREGC_DRAMC_DRCST1 ((JREG *) 0xF300000A) +#define JREGC_DRAMC_DRCST2 ((JREG *) 0xF300000C) +#define JREGC_DRAMC_DRCR ((JREG *) 0xF300000E) +#define JREGC_DRAMC_DRCS ((JREG *) 0xF3000020) +#define JREGC_DRAMC_DRASR ((JREG *) 0xF3000030) +#define JREGC_DRAMC_DRIMS1 ((JREG *) 0xF3000042) +#define JREGC_DRAMC_DRIMS2A1 ((JREG *) 0xF3000044) +#define JREGC_DRAMC_DRIMS3A2 ((JREG *) 0xF3000046) +#define JREGC_DRAMC_DRIMS4 ((JREG *) 0xF3000048) +#define JREGC_DRAMC_DRIMS5 ((JREG *) 0xF300004A) +#define JREGC_DRAMC_DRIMS6 ((JREG *) 0xF300004C) +#define JREGC_DRAMC_DRIMS7D1 ((JREG *) 0xF300004E) +#define JREGC_DRAMC_DRIMS8D2 ((JREG *) 0xF3000050) +#define JREGC_DRAMC_DRIMS9T1 ((JREG *) 0xF3000052) +#define JREGC_DRAMC_DRIMSS10T2 ((JREG *) 0xF3000054) +#define JREGC_DRAMC_DROS ((JREG *) 0xF3000060) +#define JREGC_DRAMC_DRIBSLI ((JREG *) 0xF3000062) +#define JREGC_DRAMC_DRIBSODT1 ((JREG *) 0xF3000064) +#define JREGC_DRAMC_DRIBSOCD ((JREG *) 0xF3000066) +#define JREGC_DRAMC_DRIBSOCD2 ((JREG *) 0xF3000068) +#define JREGC_DRAMC_DROABA ((JREG *) 0xF3000070) +#define JREGC_DRAMC_DROBV ((JREG *) 0xF3000080) +#define JREGC_DRAMC_DROBS ((JREG *) 0xF3000084) +#define JREGC_DRAMC_DROBSR1 ((JREG *) 0xF3000086) +#define JREGC_DRAMC_DROBSR2 ((JREG *) 0xF3000088) +#define JREGC_DRAMC_DROBSR3 ((JREG *) 0xF300008A) +#define JREGC_DRAMC_DROBSR4 ((JREG *) 0xF300008C) +#define JREGC_DRAMC_DRIMR1 ((JREG *) 0xF3000090) +#define JREGC_DRAMC_DRIMR2 ((JREG *) 0xF3000092) +#define JREGC_DRAMC_DRIMR3 ((JREG *) 0xF3000094) +#define JREGC_DRAMC_DRIMR4 ((JREG *) 0xF3000096) +#define JREGC_DRAMC_DROISR1 ((JREG *) 0xF3000098) +#define JREGC_DRAMC_DROISR2 ((JREG *) 0xF300009A) + +/* + * REGISTER ADDRESS DEFINITION FOR GPIO PERIPHERAL + */ +/* GPIO Port data register */ +#define GPIO_PORT_DATA 0x00 +/* GPIO Data Direction */ +#define GPIO_DIRECTION 0x10 + +/* GPIO Block Defines */ +#define GPIO_BLOCK_0 0x00 +#define GPIO_BLOCK_1 0x04 +#define GPIO_BLOCK_2 0x08 + +/* + * JADE Chip Control Module + * + */ + +#define CCNT_CGPIO_IST 0x18 +#define CCNT_CGPIO_ISTM 0x1c +#define CCNT_CGPIO_IP 0x20 +#define CCNT_CGPIO_IM 0x24 +#define CCNT_CMUX_MD 0x30 + +/* + * REGISTER ADDRESS DEFINITION FOR UART0 PERIPHERAL + * +#define JREGC_UART0_URT0RFR ((JREG *) 0xFFFE1000) +#define JREGC_UART0_URT0TFR ((JREG *) 0xFFFE1000) +#define JREGC_UART0_URT0DLL ((JREG *) 0xFFFE1000) +#define JREGC_UART0_URT0IER ((JREG *) 0xFFFE1004) +#define JREGC_UART0_URT0DLM ((JREG *) 0xFFFE1004) +#define JREGC_UART0_URT0IIR ((JREG *) 0xFFFE1008) +#define JREGC_UART0_URT0FCR ((JREG *) 0xFFFE1008) +#define JREGC_UART0_URT0LCR ((JREG *) 0xFFFE100C) +#define JREGC_UART0_URT0MCR ((JREG *) 0xFFFE1010) +#define JREGC_UART0_URT0LSR ((JREG *) 0xFFFE1014) +#define JREGC_UART0_URT0MSR ((JREG *) 0xFFFE1018) +#define JREGC_UART0_URT0SCR ((JREG *) 0xFFFE101C) + +/* + * REGISTER ADDRESS DEFINITION FOR UART1 PERIPHERAL + */ +#define JREGC_UART1_URT1RFR ((JREG *) 0xFFFE2000) +#define JREGC_UART1_URT1TFR ((JREG *) 0xFFFE2000) +#define JREGC_UART1_URT1DLL ((JREG *) 0xFFFE2000) +#define JREGC_UART1_URT1IER ((JREG *) 0xFFFE2004) +#define JREGC_UART1_URT1DLM ((JREG *) 0xFFFE2004) +#define JREGC_UART1_URT1IIR ((JREG *) 0xFFFE2008) +#define JREGC_UART1_URT1FCR ((JREG *) 0xFFFE2008) +#define JREGC_UART1_URT1LCR ((JREG *) 0xFFFE200C) +#define JREGC_UART1_URT1MCR ((JREG *) 0xFFFE2010) +#define JREGC_UART1_URT1LSR ((JREG *) 0xFFFE2014) +#define JREGC_UART1_URT1MSR ((JREG *) 0xFFFE2018) +#define JREGC_UART1_URT1SCR ((JREG *) 0xFFFE201C) + +/* + * REGISTER ADDRESS DEFINITION FOR CLOCK/RESET INTERFACE + */ +#define JREGC_CRG_CRPR ((JREG *) 0xFFFE7000) +#define JREGC_CRG_CRWR ((JREG *) 0xFFFE7008) +#define JREGC_CRG_CRSR ((JREG *) 0xFFFE700C) +#define JREGC_CRG_CRDA ((JREG *) 0xFFFE7010) +#define JREGC_CRG_CRDB ((JREG *) 0xFFFE7014) +#define JREGC_CRG_CRHA ((JREG *) 0xFFFE7018) +#define JREGC_CRG_CRPA ((JREG *) 0xFFFE701C) +#define JREGC_CRG_CRPB ((JREG *) 0xFFFE7020) +#define JREGC_CRG_CRHB ((JREG *) 0xFFFE7024) +#define JREGC_CRG_CRAM ((JREG *) 0xFFFE7028) + +/* + * REGISTER BASE ADDRESS DEFINITION FOR PERIPHERAL + */ +#define JREGC_BASE_DRAM ((JREGPS_DRAMC) 0xF3000000) +#define JREGC_BASE_GPIO ((JREGPS_GPIO) 0xFFFE9000) +#define JREGC_BASE_UART0 ((JREGPS_UART0) 0xFFFE1000) +#define JREGC_BASE_UART1 ((JREGPS_UART1) 0xFFFE2000) + +#endif /* jade_H */ -- 1.5.6.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in Jade SoC 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 1/3] arm: Added " Matthias Weisser @ 2009-07-08 14:02 ` Matthias Weisser 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 3/3] arm: Added support for jadecpu board based on " Matthias Weisser 2009-07-08 21:28 ` [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in " Jean-Christophe PLAGNIOL-VILLARD 2009-07-08 21:27 ` [U-Boot] [PATCH RESEND 1/3] arm: Added support for MB86R01 'Jade' SoC Jean-Christophe PLAGNIOL-VILLARD 1 sibling, 2 replies; 11+ messages in thread From: Matthias Weisser @ 2009-07-08 14:02 UTC (permalink / raw) To: u-boot This patch adds support for the display controller in the MB86R01 'Jade' SoC. Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de> --- drivers/video/Makefile | 1 + drivers/video/cfb_console.c | 2 +- drivers/video/jadegdc.c | 192 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 194 insertions(+), 1 deletions(-) create mode 100644 drivers/video/jadegdc.c diff --git a/drivers/video/Makefile b/drivers/video/Makefile index bc00852..ad4b0c9 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -30,6 +30,7 @@ COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o COBJS-$(CONFIG_S6E63D6) += s6e63d6.o COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o +COBJS-$(CONFIG_VIDEO_JADEGDC) += jadegdc.o COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index bcafb27..e23499f --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -314,7 +314,7 @@ void console_cursor (int state); #else #define SWAP16(x) (x) #define SWAP32(x) (x) -#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) || defined(CONFIG_VIDEO_JADEGDC) #define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) ) #else #define SHORTSWAP32(x) (x) diff --git a/drivers/video/jadegdc.c b/drivers/video/jadegdc.c new file mode 100644 index 0000000..d3f68ab --- /dev/null +++ b/drivers/video/jadegdc.c @@ -0,0 +1,192 @@ +/* + * (C) Copyright 2007-2009 + * Matthias Weisser <matthias.weisser@graf-syteco.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * jade.c - Graphic interface for Fujitsu Jade integrated graphic + * controller. Derived from mb862xx.c + */ + +#include <common.h> + +#include <malloc.h> +#include <mb862xx.h> +#include <asm/io.h> +#include <video_fb.h> +#include "videomodes.h" + +/* + * 4MB (at the end of system RAM) + */ +#define VIDEO_MEM_SIZE 0x400000 + +#define GDC_HOST_BASE 0xF1FC0000 +#define GDC_DSP0_BASE 0xF1FD0000 +#define GDC_DSP1_BASE 0xF1FD2000 + +/* + * Graphic Device + */ +GraphicDevice jadegdc; + +void *video_hw_init(void) +{ + GraphicDevice *pGD = &jadegdc; + struct ctfb_res_modes var_mode[2]; + unsigned long *vid; + unsigned long div; + unsigned long dspBase[2]; + char *penv; + int bpp; + int i, j; + + memset(pGD, 0, sizeof(GraphicDevice)); + + dspBase[0] = GDC_DSP0_BASE; + dspBase[1] = GDC_DSP1_BASE; + + pGD->frameAdrs = GDC_HOST_BASE; + pGD->gdfIndex = GDF_15BIT_555RGB; + pGD->gdfBytesPP = 2; + + pGD->memSize = VIDEO_MEM_SIZE; + pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; + vid = (unsigned long *)pGD->frameAdrs; + + for (i = 0; i < 2; i++) { + char varName[32]; + u32 dcm1, dcm2, dcm3; + u16 htp, hdp, hdb, hsp, vtr, vsp, vdp; + u8 hsw, vsw; + u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1; + u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh; + + sprintf(varName, "gs_dsp_%d_param", i); + + if ((penv = getenv(varName)) == NULL) + if ((i == 1) || ((penv = getenv("videomode")) == NULL)) + continue; + + bpp = 0; + bpp = video_get_params(&var_mode[i], penv); + + if (bpp == 0) { + var_mode[i].xres = 640; + var_mode[i].yres = 480; + var_mode[i].pixclock = 39721; /* 25MHz */ + var_mode[i].left_margin = 48; + var_mode[i].right_margin = 16; + var_mode[i].upper_margin = 33; + var_mode[i].lower_margin = 10; + var_mode[i].hsync_len = 96; + var_mode[i].vsync_len = 2; + var_mode[i].sync = 0; + var_mode[i].vmode = 0; + } + + for (j = 0; j < var_mode[i].xres * var_mode[i].yres / 2; j++) + *vid++ = 0xFFFFFFFF; + + pGD->winSizeX = var_mode[i].xres; + pGD->winSizeY = var_mode[i].yres; + + /* LCD base clock is ~ 660MHZ. We do calculations in kHz */ + div = 660000 / (1000000000L / var_mode[i].pixclock); + if (div > 64) + div = 64; + + dcm1 = div << 8; + dcm2 = 0x00000000; + dcm3 = 0x00000000; + + htp = var_mode[i].left_margin + var_mode[i].xres + + var_mode[i].hsync_len + var_mode[i].right_margin; + hdp = var_mode[i].xres; + hdb = var_mode[i].xres; + hsp = var_mode[i].xres + var_mode[i].right_margin; + hsw = var_mode[i].hsync_len; + + vsw = var_mode[i].vsync_len; + vtr = var_mode[i].upper_margin + var_mode[i].yres + + var_mode[i].vsync_len + var_mode[i].lower_margin; + vsp = var_mode[i].yres + var_mode[i].lower_margin; + vdp = var_mode[i].yres; + + l2m = ( (var_mode[i].yres - 1) << ( 0)) | + (((var_mode[i].xres * 2) / 64) << (16)) | + ( (1) << (31)); + + l2em = (1 << 0) | (1 << 1); + + l2oa0 = pGD->frameAdrs; + l2da0 = pGD->frameAdrs; + l2oa1 = pGD->frameAdrs; + l2da1 = pGD->frameAdrs; + l2dx = 0; + l2dy = 0; + l2wx = 0; + l2wy = 0; + l2ww = var_mode[i].xres; + l2wh = var_mode[i].yres - 1; + + writel(dcm1, dspBase[i] + GC_DCM1); + writel(dcm2, dspBase[i] + GC_DCM2); + writel(dcm3, dspBase[i] + GC_DCM3); + + writew(htp, dspBase[i] + GC_HTP); + writew(hdp, dspBase[i] + GC_HDP); + writew(hdb, dspBase[i] + GC_HDB); + writew(hsp, dspBase[i] + GC_HSP); + writeb(hsw, dspBase[i] + GC_HSW); + + writeb(vsw, dspBase[i] + GC_VSW); + writew(vtr, dspBase[i] + GC_VTR); + writew(vsp, dspBase[i] + GC_VSP); + writew(vdp, dspBase[i] + GC_VDP); + + writel(l2m, dspBase[i] + GC_L2M); + writel(l2em, dspBase[i] + GC_L2EM); + writel(l2oa0, dspBase[i] + GC_L2OA0); + writel(l2da0, dspBase[i] + GC_L2DA0); + writel(l2oa1, dspBase[i] + GC_L2OA1); + writel(l2da1, dspBase[i] + GC_L2DA1); + writew(l2dx, dspBase[i] + GC_L2DX); + writew(l2dy, dspBase[i] + GC_L2DY); + writew(l2wx, dspBase[i] + GC_L2WX); + writew(l2wy, dspBase[i] + GC_L2WY); + writew(l2ww, dspBase[i] + GC_L2WW); + writew(l2wh, dspBase[i] + GC_L2WH); + + writel(dcm1 | (1 << 18) | (1 << 31), dspBase[i] + GC_DCM1); + } + + return pGD; +} + +/* + * Set a RGB color in the LUT + */ +void video_set_lut(unsigned int index, unsigned char r, + unsigned char g, unsigned char b) +{ + +} -- 1.5.6.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH RESEND 3/3] arm: Added support for jadecpu board based on Jade SoC 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in Jade SoC Matthias Weisser @ 2009-07-08 14:02 ` Matthias Weisser 2009-07-08 21:37 ` Jean-Christophe PLAGNIOL-VILLARD 2009-07-08 21:28 ` [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in " Jean-Christophe PLAGNIOL-VILLARD 1 sibling, 1 reply; 11+ messages in thread From: Matthias Weisser @ 2009-07-08 14:02 UTC (permalink / raw) To: u-boot This patch adds support for the jadecpu board using the MB86R01 'Jade' SoC from Fujitsu. Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 7 + board/syteco/jadecpu/Makefile | 55 ++++++ board/syteco/jadecpu/config.mk | 1 + board/syteco/jadecpu/jadecpu.c | 99 ++++++++++ board/syteco/jadecpu/lowlevel_init.S | 337 ++++++++++++++++++++++++++++++++++ include/configs/jadecpu.h | 160 ++++++++++++++++ tools/Makefile | 3 + tools/logos/syteco.bmp | Bin 0 -> 12278 bytes 10 files changed, 667 insertions(+), 0 deletions(-) create mode 100644 board/syteco/jadecpu/Makefile create mode 100644 board/syteco/jadecpu/config.mk create mode 100644 board/syteco/jadecpu/jadecpu.c create mode 100644 board/syteco/jadecpu/lowlevel_init.S create mode 100644 include/configs/jadecpu.h create mode 100644 tools/logos/syteco.bmp diff --git a/MAINTAINERS b/MAINTAINERS index 9379c7e..157f437 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -671,6 +671,10 @@ Sergey Lapin <slapin@ossfans.org> afeb9260 ARM926EJS (AT91SAM9260 SoC) +Matthias Weisser <matthias.weisser@graf-syteco.de> + + jadecpu ARM926EJS (Jade SoC) + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index f4599d6..841c3d6 --- a/MAKEALL +++ b/MAKEALL @@ -533,6 +533,7 @@ LIST_ARM9=" \ davinci_sffsdr \ davinci_sonata \ davinci_dm355evm \ + jadecpu \ " ######################################################################### diff --git a/Makefile b/Makefile index bcc81c9..0088d6d --- a/Makefile +++ b/Makefile @@ -2785,6 +2785,13 @@ at91sam9rlek_config : unconfig pm9263_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91 +######################################################################### +## Different ARM926EJ-S Systems +######################################################################### + +jadecpu_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs jadecpu syteco jade + ######################################################################## ## ARM Integrator boards - see doc/README-integrator for more info. integratorap_config \ diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile new file mode 100644 index 0000000..87d2234 --- /dev/null +++ b/board/syteco/jadecpu/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += jadecpu.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk new file mode 100644 index 0000000..c661f0b --- /dev/null +++ b/board/syteco/jadecpu/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x46000000 diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c new file mode 100644 index 0000000..51dc8f7 --- /dev/null +++ b/board/syteco/jadecpu/jadecpu.c @@ -0,0 +1,99 @@ +/* + * (c) 2009 Graf-Syteco, Matthias Weisser + * <matthias.weisser@graf-syteco.de> + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/jade.h> + +DECLARE_GLOBAL_DATA_PTR; + +void multiplex_group_init(void); +void gpio_init(void); + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{ + printf("Boot reached stage %d\n", progress); +} +#endif + +static inline void delay(unsigned long loops) +{ + __asm__ volatile ("1:\n" + "subs %0, %1, #1\n" + "bne 1b" : "=r" (loops) : "0" (loops)); +} + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init(void) +{ + /* arch number of Versatile Board */ + gd->bd->bi_arch_number = 0 /*MACH_TYPE_GSJADECPU*/; + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x47000000; + + gd->flags = 0; + + icache_enable(); + + /* set Multiplex Group */ + multiplex_group_init(); + + /* init GPIOs */ + gpio_init(); + + return 0; +} + +int misc_init_r(void) +{ + setenv("verify", "n"); + return 0; +} + +/* + * DRAM configuration + */ +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + + return 0; +} + +/* + * Initial the Pin Multiplex Groups + */ +void multiplex_group_init(void) +{ + +} + +void gpio_init(void) +{ + +} + diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S new file mode 100644 index 0000000..727eda5 --- /dev/null +++ b/board/syteco/jadecpu/lowlevel_init.S @@ -0,0 +1,337 @@ +/* + * Board specific setup info + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> + * + * (C) Copyright 2003, ARM Ltd. + * Philippe Robin, <philippe.robin@arm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software/* you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation/* either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY/* without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program/* if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: +/* + * Initialize Clock Reset Generator (CRG) + */ + + ldr r0, =0xfffe7000 /* CRG base address */ + + /* Not change the initial value that is set by external pin.*/ +1: ldr r2, [r0, #0x00] /* Wait for PLLREADY */ + tst r2, #0x00000100 + beq 1b + + /* Set clock gate control */ + ldr r1, =0x0000ffff /* Open */ + str r1, [r0, #0x18] /* CRHA: AHB clock */ + ldr r1, =0x0000ffff /* Open */ + str r1, [r0, #0x1c] /* CRPA: APB-A clock */ + ldr r1, =0xfffffffe /* Close */ + str r1, [r0, #0x20] /* CRPA: APB-B clock */ + ldr r1, =0x0000ffff /* Open */ + str r1, [r0, #0x24] /* CRHB: ExtAHB clock */ + ldr r1, =0xffffffef /* Open ARM926EJ-S only */ + str r1, [r0, #0x28] /* CRAM: ARM core clock */ + +/* + * Initialize External Bus Interface + */ +#define MEMC_BASE 0xfffc0000 + + ldr r0, =MEMC_BASE /* MEMC base address */ + + /* + * SRAM/flash _mode_ registers (XCS4 is set by external pin) + * XCS0: Ethernet Controller + * XCS2: not used (?) + * XCS4: Flash + */ + ldr r1, =0x00000001 /* XCS0: 16bit */ + str r1, [r0, #0x00] + ldr r1, =0x00000001 /* XCS2: 16bit */ + str r1, [r0, #0x08] + ldr r1, =0x00000021 /* XCS4: 16bit, */ + str r1, [r0, #0x10] + + /* SRAM/flash _timing_ registers (HCLK=83.3/80MHz) */ + ldr r1, =0x055ff00f /* XCS0: */ + str r1, [r0, #0x20] + ldr r1, =0x03061008 /* XCS2: not used */ + str r1, [r0, #0x28] + ldr r1, =0x03061804 /* XCS4: FLASH ROM */ + str r1, [r0, #0x30] + + /* SRAM/flash _area_ registers (address of XCS4 is set by hardware) */ + ldr r1, =0x00000020 + str r1, [r0, #0x40] + ldr r1, =0x00000050 /* XCS2: 0x05000000/2MB */ + str r1, [r0, #0x48] + ldr r1, =0x001f0000 /* XCS4: 32 MB */ + str r1, [r0, #0x50] + +/* + * GPIO Settings + */ + +/* + * Initialize DDR2 Controller + */ +#define CCNT_BASE 0xfff42000 +#define CDEBUG1 0xec + +#define DDR2C_BASE 0xf3000000 +#define DRIC 0x00 +#define DRIC1 0x02 +#define DRIC2 0x04 +#define DRCA 0x06 +#define DRCM 0x08 +#define DRCST1 0x0a +#define DRCST2 0x0c +#define DRCR 0x0e +#define DRCF 0x20 +#define DRASR 0x30 +#define DRIMS 0x50 +#define DROS 0x60 +#define DRIBSLI 0x62 +#define DRIBSODT1 0x64 +#define DRIBSOCD 0x66 +#define DRIBSOCD2 0x68 +#define DROABA 0x70 +#define DROBV 0x80 +#define DROBS 0x84 +#define DROBSR1 0x86 +#define DROBSR2 0x88 +#define DROBSR3 0x8a +#define DROBSR4 0x8c +#define DRIMR1 0x90 +#define DRIMR2 0x92 +#define DRIMR3 0x94 +#define DRIMR4 0x96 +#define DROISR1 0x98 +#define DROISR2 0x9a + + .macro wait, count + mov r4, #\count +3: + subs r4, r4, #0x1 + bne 3b + + .endm + + /* Wait for PLL LOCK up time or more */ + wait 20 + + /* + * (2) Initialize DDRIF + */ + ldr r0, =DDR2C_BASE /* DDR2C base address */ + ldr r1, =0x5555 + strh r1, [r0, #DRIMS] + + /* + * (3) Wait for 20MCKPs(120nsec) or more + */ + wait 20 + + /* + * (4) IRESET/IUSRRST release + /* + ldr r0, =CCNT_BASE /* CCNT base address */ + ldr r1, =0x00000002 + str r1, [r0, #CDEBUG1] + + /* + * (5) Wait for 20MCKPs(120nsec) or more + */ + wait 20 + + /* + * (6) IDLLRST release + */ + ldr r0, =CCNT_BASE /* CCNT base address */ + ldr r1, =0x00000003 + str r1, [r0, #CDEBUG1] + + /* + * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec) + */ + wait 33536 + + /* + * (9) MCKE ON + */ + ldr r0, =DDR2C_BASE /* DDR2C base address */ + ldr r1, =0x003f + strh r1, [r0, #DRIC1] + ldr r1, =0x0000 + strh r1, [r0, #DRIC2] + ldr r1, =0xc124 /* 512Mbit DDR2SDRAM x 2 */ + strh r1, [r0, #DRCA] + ldr r1, =0xc000 + strh r1, [r0, #DRIC] + + /* + * (10) Initialize SDRAM + */ + ldr r0, =DDR2C_BASE /* DDR2C base address */ + ldr r1, =0xc001 /* NOP Command */ + strh r1, [r0, #DRIC] + + wait 67 /* 400ns wait */ + + ldr r1, =0x0017 /* PALL Command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0400 + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0006 /* EMR(2) command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0000 + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0007 /* EMR(3) command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0000 + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0005 /* EMR(1) command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0000 /* Extended Mode Register 1 clear*/ + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0004 /* MRS command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0532 /* Mode Register */ + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + wait 200 + + ldr r1, =0x0017 /* PALL command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0400 + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x000f /* REF command 1 */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0000 /* (changed) */ + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + wait 18 /* 105ns wait */ + + ldr r1, =0x0004 /* MRS command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0432 + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + wait 200 /* MRS to OCD: 200clock */ + + ldr r1, =0x0005 /* EMR(1) command */ + strh r1, [r0, #DRIC1] + ldr r1, =0x0380 /* Extended Mode Register 1 set OCD */ + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0005 /* EMR(1) command */ + strh r1, [r0, #DRIC1] + /* ldr r1, =0x0044 */ + ldr r1, =0x0002 /* EMR(1) set reduced strength */ + strh r1, [r0, #DRIC2] + ldr r1, =0xc001 + strh r1, [r0, #DRIC] + + ldr r1, =0x0032 /* Set BT, AL, CL, BL */ + strh r1, [r0, #DRCM] + + ldr r1, =0x3418 /* Set tRCD, tRAS, tRP, tRC */ + strh r1, [r0, #DRCST1] + + /* ldr r1, =0x2e22 */ /* Set tRFC, tRRD, tWR */ + ldr r1, =0x6e32 + strh r1, [r0, #DRCST2] + + /* ldr r1, =0x0051 */ /* Set CNTL, REF_CNT*/ + ldr r1, =0x0141 /* (changed) */ + strh r1, [r0, #DRCR] + + ldr r1, =0x0002 /* Set Address FIFO (8 steps) */ + strh r1, [r0, #DRCF] + + ldr r1, =0x0001 /* Enable AXI Cache */ + strh r1, [r0, #DRASR] + + /* + * (11) ODT setting + */ + ldr r0, =DDR2C_BASE /* DDR2C base address */ + ldr r1, =0x0001 + strh r1, [r0, #DROBS] + ldr r1, =0x0103 /* ODT auto adjustment on */ + strh r1, [r0, #DROABA] + ldr r1, =0x003F /* Set ODT to on 50/100 Ohm */ + strh r1, [r0, #DRIBSODT1] + + /* + * (12) Shift to ODTCONT ON (SDRAM side) and DDR2C usual operation mode + */ + ldr r0, =DDR2C_BASE /* DDR2C base address */ + ldr r1, =0x0001 + strh r1, [r0, #DROS] + ldr r1, =0x4000 + strh r1, [r0, #DRIC] + + mov pc, lr + +/* + * Reset CPU by writing SWRSTREQ to CRSR-register + */ +.globl reset_cpu +reset_cpu: + ldr r0, =0xfffe7000 /* CRG Base address */ + ldr r2, =0x00000002 /* SWRSTREQ */ + str r2, [r0, #0x0c] + +_loop_forever: + b _loop_forever + diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h new file mode 100644 index 0000000..235d0b6 --- /dev/null +++ b/include/configs/jadecpu.h @@ -0,0 +1,160 @@ +/* + * (C) Copyright 2007-2008 + * Matthias Weisser <matthias.weisser@graf-syteco.de> + * + * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_JADE_IOCLK (41500000) +#define CONFIG_SYS_TIMERBASE 0xfffe0000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Hardware drivers + */ + +/* + * Serial + */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK CONFIG_JADE_IOCLK +#define CONFIG_SYS_NS16550_COM1 0xfffe1000 +#define CONFIG_SYS_NS16550_COM2 0xfffe2000 + +#define CONFIG_CONS_INDEX 1 + +/* + * Ethernet + */ +#define CONFIG_DRIVER_SMC911X 1 +#define CONFIG_DRIVER_SMC911X_BASE 0x02000000 +#define CONFIG_DRIVER_SMC911X_16_BIT + +/* + * Video + */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_JADEGDC +#define CONFIG_CFB_CONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_LOGO +#define VIDEO_KBD_INIT_FCT 0 +#define VIDEO_TSTC_FCT serial_tstc +#define VIDEO_GETC_FCT serial_getc + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_IMI 1 +#define CONFIG_CMD_ELF 1 +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_BMP 1 +/* #define CONFIG_CMD_USB 1 */ + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */ +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (128 * 1024) + +/* + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */ + +#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "jade> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_BOOTDELAY 2 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif /* __CONFIG_H */ + diff --git a/tools/Makefile b/tools/Makefile index 43c284c..456e9dd --- a/tools/Makefile +++ b/tools/Makefile @@ -125,6 +125,9 @@ endif ifeq ($(VENDOR),ronetix) LOGO_BMP= logos/ronetix.bmp endif +ifeq ($(VENDOR),syteco) +LOGO_BMP= logos/syteco.bmp +endif # now $(obj) is defined SRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) diff --git a/tools/logos/syteco.bmp b/tools/logos/syteco.bmp new file mode 100644 index 0000000000000000000000000000000000000000..141ee8e10edd85caa52b9501e3a4381b81fe772d GIT binary patch literal 12278 zcmeI0TdvbE5Qg2PNJwmiH{MtP??`Ncopb>#s;lC)jN^<mx5VSvEtQTf72hWQzx=+$ zhaW%xehW+behuL(l>Wf)7yK^a^U at yw`TZsRu;KA|g!}yt)yLX&3%A>CEstzCFdP^T zd`t(f&J=<Se1cz6Vz2%xn8}kC7#8>(XPCrZWxxz)aQVUR*)s#%*H9UWBXrEA1QO&t zYstvm(XSvSGDIqb%bIEx at j1x-j~>EAlo=D;a@~oAc7b6ib0rJDLd at MXyUuWw7M5lh zfih3b_~Yq<Q0mM4sm&RQGEdX7KJAq(ZPTPs8d(~qNu#u~oQ5$_npsY+84IPE<=mPv zQ97`kn5KBBu^pKzRr@FeV}ujV0E-%key8+JPwjR%PSg-fL+v?Zuuzm~N*8k07B$EL zgOci{u%n!(&w*xPvQV*M3>M{ZnIT6kFp5Q@?7&zo5+*A-3K2%KXp{&O|B7Qh)*L|? zpC$*w76J<5c_x at E8fJ%u!)!vHl9NR{v&%xA at eq(0pD%ivp1}fG^iANr-ANEg*UW!q z5!3Wi7BY`!(b&_ei5$V^gNKdw934IaoiAk}Vud1NtB)*p`12iK3IL=Vr3MQz1&YHL z?g!T5(G$}<te52r@ir{UnfLG|IrA<o(V5;X`SwN+d0eDBdHS-))l0rbu^5}`5<7SE zRg$sjdj!8hEd8L`mjx~<>uXXIGz-iLz0M#^oeMge`4T14zy+4)zzCKVrZ7jqYdS;U zK)-geMY1HAGK&er_EJ$=1t^vU#=&C1z*A)XDyd=veR|!7ux30g3PzkUMQIhlSTc-@ zMZgG@*7F4qsH=~K!AO*L798Qkj$n(W{oIW!FU?{FOAaOLb{j}7ih~CEHp_s~Z*R(> z0tFpD&{ka*OeKq?NOh&;XfR-ESl~bKOcsZ-5uyjHVwp at 9L&w#mVCq;V!xxvX86;tv zS at 1$`sudaqOe;&gcN7#4x;acE%W?(k1=GfoP<lDj#DXX-Fy!*w!m^>X!E6i4`vtgM zK%4GqiqZ>a!!mBRTo7yU$TR*rpd^+A%JbZc6eD%0s`up(SQ{|tgv^IC(h;nGKxaB^ J$T5U;;2&8xIXwUX literal 0 HcmV?d00001 -- 1.5.6.3 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH RESEND 3/3] arm: Added support for jadecpu board based on Jade SoC 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 3/3] arm: Added support for jadecpu board based on " Matthias Weisser @ 2009-07-08 21:37 ` Jean-Christophe PLAGNIOL-VILLARD 2009-07-09 6:43 ` Matthias Weisser 0 siblings, 1 reply; 11+ messages in thread From: Jean-Christophe PLAGNIOL-VILLARD @ 2009-07-08 21:37 UTC (permalink / raw) To: u-boot > +{ > + printf("Boot reached stage %d\n", progress); > +} > +#endif > + > +static inline void delay(unsigned long loops) > +{ > + __asm__ volatile ("1:\n" > + "subs %0, %1, #1\n" > + "bne 1b" : "=r" (loops) : "0" (loops)); > +} no please remove > + > +/* > + * Miscellaneous platform dependent initialisations > + */ > + > +int board_init(void) > +{ > + /* arch number of Versatile Board */ > + gd->bd->bi_arch_number = 0 /*MACH_TYPE_GSJADECPU*/; nack the arch number must be register properly > + /* adress of boot parameters */ > + gd->bd->bi_boot_params = 0x47000000; please use this style RAM_BASE + X > + > + gd->flags = 0; > + > + icache_enable(); > + > + /* set Multiplex Group */ > + multiplex_group_init(); no please remove > + > + /* init GPIOs */ > + gpio_init(); no please remove > + > + return 0; > +} > + > +int misc_init_r(void) > +{ > + setenv("verify", "n"); > + return 0; > +} > + > +/* > + * DRAM configuration > + */ > +int dram_init(void) > +{ > + gd->bd->bi_dram[0].start = PHYS_SDRAM; > + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; > + > + return 0; > +} > + > +/* > + * Initial the Pin Multiplex Groups > + */ > +void multiplex_group_init(void) > +{ > + > +} > + > +void gpio_init(void) > +{ > + > +} > + > diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S > new file mode 100644 > index 0000000..727eda5 > --- /dev/null > +++ b/board/syteco/jadecpu/lowlevel_init.S > @@ -0,0 +1,337 @@ > +/* > + * Board specific setup info > + * > + * (C) Copyright 2007, mycable GmbH > + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> > + * > + * (C) Copyright 2007, mycable GmbH > + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> > + * > + * (C) Copyright 2003, ARM Ltd. > + * Philippe Robin, <philippe.robin@arm.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software/* you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation/* either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY/* without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program/* if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <config.h> > +#include <version.h> > + > +/* Set up the platform, once the cpu has been initialized */ > +.globl lowlevel_init > +lowlevel_init: > +/* > + * Initialize Clock Reset Generator (CRG) > + */ > + > + ldr r0, =0xfffe7000 /* CRG base address */ > + > + /* Not change the initial value that is set by external pin.*/ > +1: ldr r2, [r0, #0x00] /* Wait for PLLREADY */ > + tst r2, #0x00000100 > + beq 1b > + > + /* Set clock gate control */ > + ldr r1, =0x0000ffff /* Open */ > + str r1, [r0, #0x18] /* CRHA: AHB clock */ > + ldr r1, =0x0000ffff /* Open */ > + str r1, [r0, #0x1c] /* CRPA: APB-A clock */ > + ldr r1, =0xfffffffe /* Close */ > + str r1, [r0, #0x20] /* CRPA: APB-B clock */ > + ldr r1, =0x0000ffff /* Open */ > + str r1, [r0, #0x24] /* CRHB: ExtAHB clock */ > + ldr r1, =0xffffffef /* Open ARM926EJ-S only */ > + str r1, [r0, #0x28] /* CRAM: ARM core clock */ > + > +/* > + * Initialize External Bus Interface > + */ > +#define MEMC_BASE 0xfffc0000 > + > + ldr r0, =MEMC_BASE /* MEMC base address */ > + > + /* > + * SRAM/flash _mode_ registers (XCS4 is set by external pin) > + * XCS0: Ethernet Controller > + * XCS2: not used (?) > + * XCS4: Flash > + */ > + ldr r1, =0x00000001 /* XCS0: 16bit */ > + str r1, [r0, #0x00] > + ldr r1, =0x00000001 /* XCS2: 16bit */ > + str r1, [r0, #0x08] > + ldr r1, =0x00000021 /* XCS4: 16bit, */ > + str r1, [r0, #0x10] > + > + /* SRAM/flash _timing_ registers (HCLK=83.3/80MHz) */ > + ldr r1, =0x055ff00f /* XCS0: */ > + str r1, [r0, #0x20] > + ldr r1, =0x03061008 /* XCS2: not used */ > + str r1, [r0, #0x28] > + ldr r1, =0x03061804 /* XCS4: FLASH ROM */ > + str r1, [r0, #0x30] > + > + /* SRAM/flash _area_ registers (address of XCS4 is set by hardware) */ > + ldr r1, =0x00000020 > + str r1, [r0, #0x40] > + ldr r1, =0x00000050 /* XCS2: 0x05000000/2MB */ > + str r1, [r0, #0x48] > + ldr r1, =0x001f0000 /* XCS4: 32 MB */ > + str r1, [r0, #0x50] > + > +/* > + * GPIO Settings > + */ > + > +/* > + * Initialize DDR2 Controller > + */ > +#define CCNT_BASE 0xfff42000 please move define to proper header > +#define CDEBUG1 0xec > + > +#define DDR2C_BASE 0xf3000000 > +#define DRIC 0x00 > +#define DRIC1 0x02 > +#define DRIC2 0x04 > +#define DRCA 0x06 > +#define DRCM 0x08 > +#define DRCST1 0x0a > +#define DRCST2 0x0c > +#define DRCR 0x0e > +#define DRCF 0x20 > +#define DRASR 0x30 > +#define DRIMS 0x50 > +#define DROS 0x60 > +#define DRIBSLI 0x62 > +#define DRIBSODT1 0x64 > +#define DRIBSOCD 0x66 > +#define DRIBSOCD2 0x68 > +#define DROABA 0x70 > +#define DROBV 0x80 > +#define DROBS 0x84 > +#define DROBSR1 0x86 > +#define DROBSR2 0x88 > +#define DROBSR3 0x8a > +#define DROBSR4 0x8c > +#define DRIMR1 0x90 > +#define DRIMR2 0x92 > +#define DRIMR3 0x94 > +#define DRIMR4 0x96 > +#define DROISR1 0x98 > +#define DROISR2 0x9a what is this define? > + > + .macro wait, count > + mov r4, #\count > +3: > + subs r4, r4, #0x1 > + bne 3b > + > + .endm please use include/asm-arm/macro.h > + > + /* Wait for PLL LOCK up time or more */ > + wait 20 > + > + /* > + * (2) Initialize DDRIF > + */ > + ldr r0, =DDR2C_BASE /* DDR2C base address */ > + ldr r1, =0x5555 > + strh r1, [r0, #DRIMS] > + > + /* > + * (3) Wait for 20MCKPs(120nsec) or more > + */ > + wait 20 > + > + /* > + * (4) IRESET/IUSRRST release > + /* > + ldr r0, =CCNT_BASE /* CCNT base address */ > + ldr r1, =0x00000002 > + str r1, [r0, #CDEBUG1] > + > + /* > + * (5) Wait for 20MCKPs(120nsec) or more > + */ > + wait 20 > + > + /* > + * (6) IDLLRST release > + */ > + ldr r0, =CCNT_BASE /* CCNT base address */ > + ldr r1, =0x00000003 > + str r1, [r0, #CDEBUG1] > + > + /* > + * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec) > + */ > + wait 33536 > + > + /* > + * (9) MCKE ON > + */ > + ldr r0, =DDR2C_BASE /* DDR2C base address */ > + ldr r1, =0x003f > + strh r1, [r0, #DRIC1] > + ldr r1, =0x0000 > + strh r1, [r0, #DRIC2] > + ldr r1, =0xc124 /* 512Mbit DDR2SDRAM x 2 */ > + strh r1, [r0, #DRCA] > + ldr r1, =0xc000 > + strh r1, [r0, #DRIC] > + > + /* > + * (10) Initialize SDRAM > + */ > + ldr r0, =DDR2C_BASE /* DDR2C base address */ > + ldr r1, =0xc001 /* NOP Command */ > + strh r1, [r0, #DRIC] > + > + wait 67 /* 400ns wait */ > + > + ldr r1, =0x0017 /* PALL Command */ > + strh r1, [r0, #DRIC1] > + ldr r1, =0x0400 > + strh r1, [r0, #DRIC2] > + ldr r1, =0xc001 > + strh r1, [r0, #DRIC] > + > + ldr r1, =0x0006 /* EMR(2) command */ > + strh r1, [r0, #DRIC1] > + ldr r1, =0x0000 > + strh r1, [r0, #DRIC2] > + ldr r1, =0xc001 > + strh r1, [r0, #DRIC] > + > + ldr r1, =0x0007 /* EMR(3) command */ > + strh r1, [r0, #DRIC1] > + ldr r1, =0x0000 > + strh r1, [r0, #DRIC2] > + ldr r1, =0xc001 > + strh r1, [r0, #DRIC] > + > + ldr r1, =0x0005 /* EMR(1) command */ > + strh r1, [r0, #DRIC1] > + ldr r1, =0x0000 /* Extended Mode Register 1 clear*/ > + strh r1, [r0, #DRIC2] > + ldr r1, =0xc001 > + strh r1, [r0, #DRIC] > + > + ldr r1, =0x0004 /* MRS command */ > + strh r1, [r0, #DRIC1] > + ldr r1, =0x0532 /* Mode Register */ > + strh r1, [r0, #DRIC2] > + ldr r1, =0xc001 > + strh r1, [r0, #DRIC] > + > + wait 200 > + > + ldr r1, =0x0017 /* PALL command */ > + strh r1, [r0, #DRIC1] > + ldr r1, =0x0400 > + strh r1, [r0, #DRIC2] > + ldr r1, =0xc001 > + strh r1, [r0, #DRIC] > + > + ldr r1, =0x000f /* REF command 1 */ > + strh r1, [r0, #DRIC1] > + ldr r1, =0x0000 /* (changed) */ > + strh r1, [r0, #DRIC2] > + ldr r1, =0xc001 > + strh r1, [r0, #DRIC] > + > + wait 18 /* 105ns wait */ > + > + ldr r1, =0x0004 /* MRS command */ > + strh r1, [r0, #DRIC1] > + ldr r1, =0x0432 > + strh r1, [r0, #DRIC2] > + ldr r1, =0xc001 > + strh r1, [r0, #DRIC] > + > + wait 200 /* MRS to OCD: 200clock */ > + > + ldr r1, =0x0005 /* EMR(1) command */ > + strh r1, [r0, #DRIC1] > + ldr r1, =0x0380 /* Extended Mode Register 1 set OCD */ > + strh r1, [r0, #DRIC2] > + ldr r1, =0xc001 > + strh r1, [r0, #DRIC] > + > + ldr r1, =0x0005 /* EMR(1) command */ > + strh r1, [r0, #DRIC1] > + /* ldr r1, =0x0044 */ > + ldr r1, =0x0002 /* EMR(1) set reduced strength */ > + strh r1, [r0, #DRIC2] > + ldr r1, =0xc001 > + strh r1, [r0, #DRIC] > + > + ldr r1, =0x0032 /* Set BT, AL, CL, BL */ > + strh r1, [r0, #DRCM] > + > + ldr r1, =0x3418 /* Set tRCD, tRAS, tRP, tRC */ > + strh r1, [r0, #DRCST1] > + > + /* ldr r1, =0x2e22 */ /* Set tRFC, tRRD, tWR */ > + ldr r1, =0x6e32 > + strh r1, [r0, #DRCST2] > + > + /* ldr r1, =0x0051 */ /* Set CNTL, REF_CNT*/ > + ldr r1, =0x0141 /* (changed) */ > + strh r1, [r0, #DRCR] > + > + ldr r1, =0x0002 /* Set Address FIFO (8 steps) */ > + strh r1, [r0, #DRCF] > + > + ldr r1, =0x0001 /* Enable AXI Cache */ > + strh r1, [r0, #DRASR] > + > + /* > + * (11) ODT setting > + */ > + ldr r0, =DDR2C_BASE /* DDR2C base address */ > + ldr r1, =0x0001 > + strh r1, [r0, #DROBS] > + ldr r1, =0x0103 /* ODT auto adjustment on */ > + strh r1, [r0, #DROABA] > + ldr r1, =0x003F /* Set ODT to on 50/100 Ohm */ > + strh r1, [r0, #DRIBSODT1] > + > + /* > + * (12) Shift to ODTCONT ON (SDRAM side) and DDR2C usual operation mode > + */ > + ldr r0, =DDR2C_BASE /* DDR2C base address */ > + ldr r1, =0x0001 > + strh r1, [r0, #DROS] > + ldr r1, =0x4000 > + strh r1, [r0, #DRIC] > + > + mov pc, lr > + > +/* > + * Reset CPU by writing SWRSTREQ to CRSR-register > + */ > +.globl reset_cpu > +reset_cpu: > + ldr r0, =0xfffe7000 /* CRG Base address */ > + ldr r2, =0x00000002 /* SWRSTREQ */ > + str r2, [r0, #0x0c] > + > +_loop_forever: > + b _loop_forever is it board or soc specific reset? this ram init is board or soc specific? > + > diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h > new file mode 100644 > index 0000000..235d0b6 > --- /dev/null > +++ b/include/configs/jadecpu.h > @@ -0,0 +1,160 @@ > +/* > + * (C) Copyright 2007-2008 > + * Matthias Weisser <matthias.weisser@graf-syteco.de> > + * > + * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#define CONFIG_SHOW_BOOT_PROGRESS 1 > + > +#define CONFIG_SYS_HZ 1000 > +#define CONFIG_JADE_IOCLK (41500000) > +#define CONFIG_SYS_TIMERBASE 0xfffe0000 I guess it's soc specific so please move it to proper header > + > +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ > +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ > + > +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ > +#define CONFIG_SETUP_MEMORY_TAGS 1 > +#define CONFIG_INITRD_TAG 1 > + > +/* > + * Hardware drivers > + */ > + > +/* > + * Serial > + */ > +#define CONFIG_SYS_NS16550 > +#define CONFIG_SYS_NS16550_SERIAL > +#define CONFIG_SYS_NS16550_REG_SIZE (-4) > +#define CONFIG_SYS_NS16550_CLK CONFIG_JADE_IOCLK > +#define CONFIG_SYS_NS16550_COM1 0xfffe1000 > +#define CONFIG_SYS_NS16550_COM2 0xfffe2000 > + > +#define CONFIG_CONS_INDEX 1 > + > +/* > + * Ethernet > + */ > +#define CONFIG_DRIVER_SMC911X 1 > +#define CONFIG_DRIVER_SMC911X_BASE 0x02000000 > +#define CONFIG_DRIVER_SMC911X_16_BIT > + > +/* > + * Video > + */ > +#define CONFIG_VIDEO > +#define CONFIG_VIDEO_JADEGDC > +#define CONFIG_CFB_CONSOLE > +#define CONFIG_SYS_CONSOLE_IS_IN_ENV > +#define CONFIG_VIDEO_LOGO > +#define CONFIG_SPLASH_SCREEN > +#define CONFIG_VIDEO_BMP_LOGO > +#define VIDEO_KBD_INIT_FCT 0 > +#define VIDEO_TSTC_FCT serial_tstc > +#define VIDEO_GETC_FCT serial_getc ?? why? > + > +/* > + * BOOTP options > + */ > +#define CONFIG_BOOTP_BOOTFILESIZE 1 > +#define CONFIG_BOOTP_BOOTPATH 1 > +#define CONFIG_BOOTP_GATEWAY 1 > +#define CONFIG_BOOTP_HOSTNAME 1 > + > +/* > + * Command line configuration. > + */ > +#include <config_cmd_default.h> > +#undef CONFIG_CMD_BDI > +#undef CONFIG_CMD_FPGA > +#undef CONFIG_CMD_IMI > +#undef CONFIG_CMD_IMLS > +#undef CONFIG_CMD_LOADS > +#undef CONFIG_CMD_SOURCE > + > +#define CONFIG_CMD_IMI 1 > +#define CONFIG_CMD_ELF 1 > +#define CONFIG_CMD_PING 1 > +#define CONFIG_CMD_DHCP 1 > +#define CONFIG_CMD_BMP 1 > +/* #define CONFIG_CMD_USB 1 */ please no dead code Best Regards, J. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH RESEND 3/3] arm: Added support for jadecpu board based on Jade SoC 2009-07-08 21:37 ` Jean-Christophe PLAGNIOL-VILLARD @ 2009-07-09 6:43 ` Matthias Weisser 2009-07-12 15:50 ` Jean-Christophe PLAGNIOL-VILLARD 0 siblings, 1 reply; 11+ messages in thread From: Matthias Weisser @ 2009-07-09 6:43 UTC (permalink / raw) To: u-boot Hello Jean-Christophe >> +int board_init(void) >> +{ >> + /* arch number of Versatile Board */ >> + gd->bd->bi_arch_number = 0 /*MACH_TYPE_GSJADECPU*/; > nack How to get a arch number? As I don't use Linux on that board I don't think I need one. What is the right way to handle such a situation? Dont't set bi_arch_number at all? >> +#define CCNT_BASE 0xfff42000 > please move define to proper header >> +#define CDEBUG1 0xec >> + >> +#define DDR2C_BASE 0xf3000000 >> +#define DRIC 0x00 >> +#define DRIC1 0x02 >> +#define DRIC2 0x04 >> +#define DRCA 0x06 >> +#define DRCM 0x08 >> +#define DRCST1 0x0a >> +#define DRCST2 0x0c >> +#define DRCR 0x0e >> +#define DRCF 0x20 >> +#define DRASR 0x30 >> +#define DRIMS 0x50 >> +#define DROS 0x60 >> +#define DRIBSLI 0x62 >> +#define DRIBSODT1 0x64 >> +#define DRIBSOCD 0x66 >> +#define DRIBSOCD2 0x68 >> +#define DROABA 0x70 >> +#define DROBV 0x80 >> +#define DROBS 0x84 >> +#define DROBSR1 0x86 >> +#define DROBSR2 0x88 >> +#define DROBSR3 0x8a >> +#define DROBSR4 0x8c >> +#define DRIMR1 0x90 >> +#define DRIMR2 0x92 >> +#define DRIMR3 0x94 >> +#define DRIMR4 0x96 >> +#define DROISR1 0x98 >> +#define DROISR2 0x9a > what is this define? I will check this and move the needed ones to jade.h >> + >> + .macro wait, count >> + mov r4, #\count >> +3: >> + subs r4, r4, #0x1 >> + bne 3b >> + >> + .endm > please use include/asm-arm/macro.h I don't have this file here. Is it currently included in the master branch of u-boot? >> +/* >> + * Reset CPU by writing SWRSTREQ to CRSR-register >> + */ >> +.globl reset_cpu >> +reset_cpu: >> + ldr r0, =0xfffe7000 /* CRG Base address */ >> + ldr r2, =0x00000002 /* SWRSTREQ */ >> + str r2, [r0, #0x0c] >> + >> +_loop_forever: >> + b _loop_forever > is it board or soc specific reset? Reset is soc specific. I will move it to reset.c in the soc dir. Right? > this ram init is board or soc specific? RAM init is board specific as the soc could use other RAM configurations on other boards. So I think it should stay here. >> +#define CONFIG_SYS_HZ 1000 >> +#define CONFIG_JADE_IOCLK (41500000) >> +#define CONFIG_SYS_TIMERBASE 0xfffe0000 > I guess it's soc specific so please move it to proper header For the timer base, yes. >> +#define VIDEO_KBD_INIT_FCT 0 >> +#define VIDEO_TSTC_FCT serial_tstc >> +#define VIDEO_GETC_FCT serial_getc > ?? > why? Well, copy + paste from other board. Even if video is stdout/stdin serial port is used for input. Better way would be...? I will fix the points from the other mails also. Thanks for your time, Matthias ------------------------------------ Amtsgericht Freiburg HRA 602707 Ust. ID-Nr.: DE232464428 Gesch?ftsf?hrer: Dipl. Ing. (FH) Martin Graf Dipl. Ing. (FH) David Graf Dipl. Inf. Fabian Graf Komplement?rin: GRAF-SYTECO Verwaltungs-GmbH Amtsgericht Freiburg HRB 602868 ------------------------------------ ^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH RESEND 3/3] arm: Added support for jadecpu board based on Jade SoC 2009-07-09 6:43 ` Matthias Weisser @ 2009-07-12 15:50 ` Jean-Christophe PLAGNIOL-VILLARD 0 siblings, 0 replies; 11+ messages in thread From: Jean-Christophe PLAGNIOL-VILLARD @ 2009-07-12 15:50 UTC (permalink / raw) To: u-boot On 08:43 Thu 09 Jul , Matthias Weisser wrote: > Hello Jean-Christophe > > >> +int board_init(void) > >> +{ > >> + /* arch number of Versatile Board */ > >> + gd->bd->bi_arch_number = 0 /*MACH_TYPE_GSJADECPU*/; > > nack > > How to get a arch number? As I don't use Linux on that board > I don't think I need one. What is the right way to handle > such a situation? Dont't set bi_arch_number at all? you have no plan to support linux? if not, just do not add it and disable linux boot support btw please put a comment in the config about it > > >> +#define CCNT_BASE 0xfff42000 > > please move define to proper header > >> +#define CDEBUG1 0xec > >> + > >> +#define DDR2C_BASE 0xf3000000 > >> +#define DRIC 0x00 > >> +#define DRIC1 0x02 > >> +#define DRIC2 0x04 > >> +#define DRCA 0x06 > >> +#define DRCM 0x08 > >> +#define DRCST1 0x0a > >> +#define DRCST2 0x0c > >> +#define DRCR 0x0e > >> +#define DRCF 0x20 > >> +#define DRASR 0x30 > >> +#define DRIMS 0x50 > >> +#define DROS 0x60 > >> +#define DRIBSLI 0x62 > >> +#define DRIBSODT1 0x64 > >> +#define DRIBSOCD 0x66 > >> +#define DRIBSOCD2 0x68 > >> +#define DROABA 0x70 > >> +#define DROBV 0x80 > >> +#define DROBS 0x84 > >> +#define DROBSR1 0x86 > >> +#define DROBSR2 0x88 > >> +#define DROBSR3 0x8a > >> +#define DROBSR4 0x8c > >> +#define DRIMR1 0x90 > >> +#define DRIMR2 0x92 > >> +#define DRIMR3 0x94 > >> +#define DRIMR4 0x96 > >> +#define DROISR1 0x98 > >> +#define DROISR2 0x9a > > what is this define? > > I will check this and move the needed ones to jade.h > > >> + > >> + .macro wait, count > >> + mov r4, #\count > >> +3: > >> + subs r4, r4, #0x1 > >> + bne 3b > >> + > >> + .endm > > please use include/asm-arm/macro.h > > I don't have this file here. Is it currently included in the > master branch of u-boot? yes > > >> +/* > >> + * Reset CPU by writing SWRSTREQ to CRSR-register > >> + */ > >> +.globl reset_cpu > >> +reset_cpu: > >> + ldr r0, =0xfffe7000 /* CRG Base address */ > >> + ldr r2, =0x00000002 /* SWRSTREQ */ > >> + str r2, [r0, #0x0c] > >> + > >> +_loop_forever: > >> + b _loop_forever > > is it board or soc specific reset? > > Reset is soc specific. I will move it to reset.c in the soc dir. > Right? yes please > > > this ram init is board or soc specific? > > RAM init is board specific as the soc could use other RAM > configurations on other boards. So I think it should stay here. > > >> +#define CONFIG_SYS_HZ 1000 > >> +#define CONFIG_JADE_IOCLK (41500000) > >> +#define CONFIG_SYS_TIMERBASE 0xfffe0000 > > I guess it's soc specific so please move it to proper header > > For the timer base, yes. > > >> +#define VIDEO_KBD_INIT_FCT 0 > >> +#define VIDEO_TSTC_FCT serial_tstc > >> +#define VIDEO_GETC_FCT serial_getc > > ?? > > why? > > Well, copy + paste from other board. Even if video is stdout/stdin > serial port is used for input. Better way would be...? please use device_t in this case and set via preboot the correct stdout/stderr you can also consider to add iomux support so you can use both at the sametime Best Regards, J. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in Jade SoC 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in Jade SoC Matthias Weisser 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 3/3] arm: Added support for jadecpu board based on " Matthias Weisser @ 2009-07-08 21:28 ` Jean-Christophe PLAGNIOL-VILLARD 2009-07-08 22:25 ` Anatolij Gustschin 1 sibling, 1 reply; 11+ messages in thread From: Jean-Christophe PLAGNIOL-VILLARD @ 2009-07-08 21:28 UTC (permalink / raw) To: u-boot On 16:02 Wed 08 Jul , Matthias Weisser wrote: > This patch adds support for the display controller in > the MB86R01 'Jade' SoC. > > Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de> > --- > drivers/video/Makefile | 1 + > drivers/video/cfb_console.c | 2 +- > drivers/video/jadegdc.c | 192 +++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 194 insertions(+), 1 deletions(-) > create mode 100644 drivers/video/jadegdc.c > > diff --git a/drivers/video/Makefile b/drivers/video/Makefile > index bc00852..ad4b0c9 > --- a/drivers/video/Makefile > +++ b/drivers/video/Makefile > @@ -30,6 +30,7 @@ COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o > COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o > COBJS-$(CONFIG_S6E63D6) += s6e63d6.o > COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o > +COBJS-$(CONFIG_VIDEO_JADEGDC) += jadegdc.o > COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o > COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o > COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o > diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c > index bcafb27..e23499f > --- a/drivers/video/cfb_console.c > +++ b/drivers/video/cfb_console.c > @@ -314,7 +314,7 @@ void console_cursor (int state); > #else > #define SWAP16(x) (x) > #define SWAP32(x) (x) > -#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) > +#if defined(VIDEO_FB_16BPP_PIXEL_SWAP) || defined(CONFIG_VIDEO_JADEGDC) > #define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) ) > #else > #define SHORTSWAP32(x) (x) > diff --git a/drivers/video/jadegdc.c b/drivers/video/jadegdc.c > new file mode 100644 > index 0000000..d3f68ab > --- /dev/null > +++ b/drivers/video/jadegdc.c > @@ -0,0 +1,192 @@ > +/* > + * (C) Copyright 2007-2009 > + * Matthias Weisser <matthias.weisser@graf-syteco.de> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +/* > + * jade.c - Graphic interface for Fujitsu Jade integrated graphic > + * controller. Derived from mb862xx.c > + */ > + > +#include <common.h> > + > +#include <malloc.h> > +#include <mb862xx.h> > +#include <asm/io.h> > +#include <video_fb.h> > +#include "videomodes.h" > + > +/* > + * 4MB (at the end of system RAM) > + */ > +#define VIDEO_MEM_SIZE 0x400000 > + > +#define GDC_HOST_BASE 0xF1FC0000 > +#define GDC_DSP0_BASE 0xF1FD0000 > +#define GDC_DSP1_BASE 0xF1FD2000 please move to a header > + > +/* > + * Graphic Device > + */ > +GraphicDevice jadegdc; please no uppercase in type Best Regards, J. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in Jade SoC 2009-07-08 21:28 ` [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in " Jean-Christophe PLAGNIOL-VILLARD @ 2009-07-08 22:25 ` Anatolij Gustschin 2009-07-08 22:43 ` Jean-Christophe PLAGNIOL-VILLARD 0 siblings, 1 reply; 11+ messages in thread From: Anatolij Gustschin @ 2009-07-08 22:25 UTC (permalink / raw) To: u-boot Jean-Christophe PLAGNIOL-VILLARD wrote: > On 16:02 Wed 08 Jul , Matthias Weisser wrote: >> This patch adds support for the display controller in >> the MB86R01 'Jade' SoC. >> >> Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de> >> --- ... >> + >> +/* >> + * 4MB (at the end of system RAM) >> + */ >> +#define VIDEO_MEM_SIZE 0x400000 >> + >> +#define GDC_HOST_BASE 0xF1FC0000 >> +#define GDC_DSP0_BASE 0xF1FD0000 >> +#define GDC_DSP1_BASE 0xF1FD2000 > please move to a header probably we should drop these entirely and use JADE_GDC_PHYS_BASE and JADE_GDC_PHYS_DISP_BASE from include/asm-arm/arch-jade/jade.h file introduced with this patch series? Just need to add the base for second display controller register block there. ... >> +GraphicDevice jadegdc; > please no uppercase in type we have to stay with GraphicDevice type in this patch now. It is there in U-Boot code since more than five years, Matthias simply uses it here as other video drivers use it, too. But yes, we should do general video code cleanup later. Best regards, Anatolij ^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in Jade SoC 2009-07-08 22:25 ` Anatolij Gustschin @ 2009-07-08 22:43 ` Jean-Christophe PLAGNIOL-VILLARD 0 siblings, 0 replies; 11+ messages in thread From: Jean-Christophe PLAGNIOL-VILLARD @ 2009-07-08 22:43 UTC (permalink / raw) To: u-boot On 00:25 Thu 09 Jul , Anatolij Gustschin wrote: > Jean-Christophe PLAGNIOL-VILLARD wrote: > > On 16:02 Wed 08 Jul , Matthias Weisser wrote: > >> This patch adds support for the display controller in > >> the MB86R01 'Jade' SoC. > >> > >> Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de> > >> --- > ... > >> + > >> +/* > >> + * 4MB (at the end of system RAM) > >> + */ > >> +#define VIDEO_MEM_SIZE 0x400000 > >> + > >> +#define GDC_HOST_BASE 0xF1FC0000 > >> +#define GDC_DSP0_BASE 0xF1FD0000 > >> +#define GDC_DSP1_BASE 0xF1FD2000 > > please move to a header > > probably we should drop these entirely and use JADE_GDC_PHYS_BASE > and JADE_GDC_PHYS_DISP_BASE from include/asm-arm/arch-jade/jade.h > file introduced with this patch series? Just need to add the > base for second display controller register block there. > > ... > >> +GraphicDevice jadegdc; > > please no uppercase in type > > we have to stay with GraphicDevice type in this patch now. It is > there in U-Boot code since more than five years, Matthias simply > uses it here as other video drivers use it, too. But yes, we should > do general video code cleanup later. ok fine Best Regards, J. ^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH RESEND 1/3] arm: Added support for MB86R01 'Jade' SoC 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 1/3] arm: Added " Matthias Weisser 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in Jade SoC Matthias Weisser @ 2009-07-08 21:27 ` Jean-Christophe PLAGNIOL-VILLARD 1 sibling, 0 replies; 11+ messages in thread From: Jean-Christophe PLAGNIOL-VILLARD @ 2009-07-08 21:27 UTC (permalink / raw) To: u-boot On 16:02 Wed 08 Jul , Matthias Weisser wrote: > This patch adds support for MB86R01 'Jade' SoC from Fujitsu > > Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de> > --- > cpu/arm926ejs/jade/Makefile | 47 +++++++++ > cpu/arm926ejs/jade/timer.c | 126 ++++++++++++++++++++++++ > include/asm-arm/arch-jade/hardware.h | 31 ++++++ > include/asm-arm/arch-jade/jade.h | 177 ++++++++++++++++++++++++++++++++++ > 4 files changed, 381 insertions(+), 0 deletions(-) > create mode 100644 cpu/arm926ejs/jade/Makefile > create mode 100644 cpu/arm926ejs/jade/timer.c > create mode 100644 include/asm-arm/arch-jade/hardware.h > create mode 100644 include/asm-arm/arch-jade/jade.h > > diff --git a/cpu/arm926ejs/jade/Makefile b/cpu/arm926ejs/jade/Makefile > new file mode 100644 > index 0000000..7da9f40 > --- /dev/null > +++ b/cpu/arm926ejs/jade/Makefile > @@ -0,0 +1,47 @@ > +# > +# (C) Copyright 2000-2006 > +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(SOC).a > + > +COBJS = timer.o > +SOBJS = > + > +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) > +START := $(addprefix $(obj),$(START)) > + > +all: $(obj).depend $(LIB) > + > +$(LIB): $(OBJS) > + $(AR) $(ARFLAGS) $@ $(OBJS) > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/cpu/arm926ejs/jade/timer.c b/cpu/arm926ejs/jade/timer.c > new file mode 100644 > index 0000000..2d262c8 > --- /dev/null > +++ b/cpu/arm926ejs/jade/timer.c > @@ -0,0 +1,126 @@ > +/* > + * (C) Copyright 2007-2008 > + * Stelian Pop <stelian.pop@leadtechdesign.com> > + * Lead Tech Design <www.leadtechdesign.com> > + * > + * Matthias Weisser <matthias.weisser@graf-syteco.de> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <div64.h> > + > +#define TIMER_LOAD_VAL 0xffffffff > +#define TIMER_BASE 0xfffe0000 whitespace please fix > + > +#define READ_TIMER (*(volatile ulong *)(TIMER_BASE+4)) > +#define TIMER_FREQ (CONFIG_JADE_IOCLK / 16) whitespace please fix > + > +static ulong timestamp; > +static ulong lastdec; > + > +static inline unsigned long long tick_to_time(unsigned long long tick) > +{ > + tick *= CONFIG_SYS_HZ; > + do_div(tick, TIMER_FREQ); > + > + return tick; > +} > + > +static inline unsigned long long usec_to_tick(unsigned long long usec) > +{ > + usec *= TIMER_FREQ; > + do_div(usec, 1000000); > + > + return usec; > +} > + > +/* nothing really to do with interrupts, just starts up a counter. */ > +int timer_init(void) > +{ > + *(volatile ulong *)(TIMER_BASE + 0) = TIMER_LOAD_VAL; > + *(volatile ulong *)(TIMER_BASE + 8) = 0x86; please use proper accessor readx/writex > + > + reset_timer_masked(); > + > + return 0; > +} > + > +/* > + * timer without interrupts > + */ > +unsigned long long get_ticks(void) > +{ > + ulong now = READ_TIMER; > + > + if (now <= lastdec) /* normal mode (non roll) */ > + /* move stamp forward with absolut diff ticks */ > + timestamp += (lastdec - now); > + else /* we have rollover of incrementer */ > + timestamp += lastdec + TIMER_LOAD_VAL - now; > + lastdec = now; > + return timestamp; > +} > + > +void reset_timer_masked(void) > +{ > + /* reset time */ > + lastdec = READ_TIMER; /* capture current decrement value time */ > + timestamp = 0; /* start "advancing" time stamp from 0 */ > +} > + > +ulong get_timer_masked(void) > +{ > + return tick_to_time(get_ticks()); > +} > + > +void udelay(unsigned long usec) > +{ > + unsigned long long tmp; > + ulong tmo; > + > + tmo = usec_to_tick(usec); > + tmp = get_ticks() + tmo; /* get current timestamp */ > + > + while (get_ticks() < tmp) /* loop till event */ > + /*NOP*/; > +} > + > +void reset_timer(void) > +{ > + reset_timer_masked(); > +} > + > +ulong get_timer(ulong base) > +{ > + return get_timer_masked() - base; > +} > + > +/* > + * This function is derived from PowerPC code (timebase clock frequency). > + * On ARM it returns the number of timer ticks per second. > + */ > +ulong get_tbclk(void) > +{ > + ulong tbclk; > + > + tbclk = CONFIG_SYS_HZ; > + return tbclk; please return it directly > +} > diff --git a/include/asm-arm/arch-jade/hardware.h b/include/asm-arm/arch-jade/hardware.h > new file mode 100644 > index 0000000..a26bdca > --- /dev/null > +++ b/include/asm-arm/arch-jade/hardware.h > @@ -0,0 +1,31 @@ > +/* > + * (C) Copyright 2007 > + * > + * Author : Carsten Schneider, mycable GmbH > + * <cs@mycable.de> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > +#ifndef __ASM_ARCH_HARDWARE_H > +#define __ASM_ARCH_HARDWARE_H > + > +#include <asm/sizes.h> > +#include <asm/arch/jade.h> > + > +#endif > diff --git a/include/asm-arm/arch-jade/jade.h b/include/asm-arm/arch-jade/jade.h > new file mode 100644 > index 0000000..c2b28a2 > --- /dev/null > +++ b/include/asm-arm/arch-jade/jade.h > @@ -0,0 +1,177 @@ > +/* > + * (C) Copyright 2007 > + * > + * jade definitions > + * > + * Author : Carsten Schneider, mycable GmbH > + * <cs@mycable.de> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef JADE_H > +#define JADE_H > + > +typedef volatile unsigned int JREG; /* Hardware register */ > + > +/* > + * Physical Address Defines > + */ > +#define JADE_GDC_PHYS_BASE 0xf1fc0000 > +#define JADE_GDC_PHYS_DISP_BASE 0xf1fd0000 > +#define JADE_CCNT_PHYS_BASE 0xfff42000 > +#define JADE_CAN0_PHYS_BASE 0xfff54000 > +#define JADE_CAN1_PHYS_BASE 0xfff55000 > +#define JADE_I2C0_PHYS_BASE 0xfff56000 > +#define JADE_I2C1_PHYS_BASE 0xfff57000 > +#define JADE_EHCI_PHYS_BASE 0xfff80000 > +#define JADE_OHCI_PHYS_BASE 0xfff81000 > +#define JADE_IRC1_PHYS_BASE 0xfffb0000 > +#define JADE_TIMER_PHYS_BASE 0xfffe0000 > +#define JADE_UART0_PHYS_BASE 0xfffe1000 > +#define JADE_UART1_PHYS_BASE 0xfffe2000 > +#define JADE_IRCE_PHYS_BASE 0xfffe4000 > +#define JADE_CRG_PHYS_BASE 0xfffe7000 > +#define JADE_IRC0_PHYS_BASE 0xfffe8000 > +#define JADE_GPIO_PHYS_BASE 0xfffe9000 please align them > + > + > +/* DRAMC_DRIC DRAM Controller Mode Register */ > + > +/* > + * REGISTER ADDRESS DEFINITION FOR DRAMC PERIPHERAL > + */ > +#define JREGC_DRAMC_DRIC ((JREG *) 0xF3000000) please remove the JREG everywhere as no need when use proper accessor Best Regards, J. ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2009-07-12 15:50 UTC | newest] Thread overview: 11+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2009-07-08 14:02 [U-Boot] [PATCH RESEND 0/3] arm: Add support for MB86R01 'Jade' SoC Matthias Weisser 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 1/3] arm: Added " Matthias Weisser 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in Jade SoC Matthias Weisser 2009-07-08 14:02 ` [U-Boot] [PATCH RESEND 3/3] arm: Added support for jadecpu board based on " Matthias Weisser 2009-07-08 21:37 ` Jean-Christophe PLAGNIOL-VILLARD 2009-07-09 6:43 ` Matthias Weisser 2009-07-12 15:50 ` Jean-Christophe PLAGNIOL-VILLARD 2009-07-08 21:28 ` [U-Boot] [PATCH RESEND 2/3] arm: added support for display controller in " Jean-Christophe PLAGNIOL-VILLARD 2009-07-08 22:25 ` Anatolij Gustschin 2009-07-08 22:43 ` Jean-Christophe PLAGNIOL-VILLARD 2009-07-08 21:27 ` [U-Boot] [PATCH RESEND 1/3] arm: Added support for MB86R01 'Jade' SoC Jean-Christophe PLAGNIOL-VILLARD
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