* Why flush_cache_all() not including flushing L2 cache if the system has L2 cache?
@ 2009-11-02 2:32 Peter Chen
2009-11-02 3:42 ` Eric Miao
2009-11-02 11:00 ` Russell King - ARM Linux
0 siblings, 2 replies; 5+ messages in thread
From: Peter Chen @ 2009-11-02 2:32 UTC (permalink / raw)
To: linux-arm-kernel
Dear list,
I met a problem if the address is first used by cachable, then
uncachable. After that, the address will be filled with cachable value
after that L2 cache line is evicted.
Thank you!
--
Best regards,
Peter Chen
^ permalink raw reply [flat|nested] 5+ messages in thread
* Why flush_cache_all() not including flushing L2 cache if the system has L2 cache?
2009-11-02 2:32 Why flush_cache_all() not including flushing L2 cache if the system has L2 cache? Peter Chen
@ 2009-11-02 3:42 ` Eric Miao
2009-11-02 10:43 ` Peter Chen
2009-11-02 11:00 ` Russell King - ARM Linux
1 sibling, 1 reply; 5+ messages in thread
From: Eric Miao @ 2009-11-02 3:42 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Nov 2, 2009 at 10:32 AM, Peter Chen <hzpeterchen@gmail.com> wrote:
> Dear list,
>
> I met a problem if the address is first used by cachable, then uncachable.
> After that, the address will be filled with cachable value
> after that L2 cache line is evicted.
>
L2 cache is usually physically tagged, and from the CPU POV, it's
consistent once the L1 is flushed.
If you have problems with L2 not being flushed, it's most likely a
device issue, which means you probably need the dma_ API.
^ permalink raw reply [flat|nested] 5+ messages in thread
* Why flush_cache_all() not including flushing L2 cache if the system has L2 cache?
2009-11-02 3:42 ` Eric Miao
@ 2009-11-02 10:43 ` Peter Chen
0 siblings, 0 replies; 5+ messages in thread
From: Peter Chen @ 2009-11-02 10:43 UTC (permalink / raw)
To: linux-arm-kernel
Eric Miao wrote:
> On Mon, Nov 2, 2009 at 10:32 AM, Peter Chen <hzpeterchen@gmail.com> wrote:
>> Dear list,
>>
>> I met a problem if the address is first used by cachable, then uncachable.
>> After that, the address will be filled with cachable value
>> after that L2 cache line is evicted.
>>
>
> L2 cache is usually physically tagged, and from the CPU POV, it's
> consistent once the L1 is flushed.
My SoC platform is arm11, and L2 is PIPT. what do you mean " from the
CPU POV, it's consistent once the L1 is flushed"?
>
> If you have problems with L2 not being flushed, it's most likely a
> device issue, which means you probably need the dma_ API.
>
I know it can be fixed by using dma_ API for alloc uncachable address.
But If someone uses uncachable memory address before flush it, it is
problem. Since L1 should be flushed at code, why L2 not?
Thank you!
--
Best regards,
Peter Chen
^ permalink raw reply [flat|nested] 5+ messages in thread
* Why flush_cache_all() not including flushing L2 cache if the system has L2 cache?
2009-11-02 2:32 Why flush_cache_all() not including flushing L2 cache if the system has L2 cache? Peter Chen
2009-11-02 3:42 ` Eric Miao
@ 2009-11-02 11:00 ` Russell King - ARM Linux
2009-11-03 3:10 ` Peter Chen
1 sibling, 1 reply; 5+ messages in thread
From: Russell King - ARM Linux @ 2009-11-02 11:00 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Nov 02, 2009 at 10:32:13AM +0800, Peter Chen wrote:
> I met a problem if the address is first used by cachable, then
> uncachable. After that, the address will be filled with cachable value
> after that L2 cache line is evicted.
What _exactly_ are you trying to do? Why are you apparantly mapping
something in as cacheable, and then making it uncacheable?
^ permalink raw reply [flat|nested] 5+ messages in thread
* Why flush_cache_all() not including flushing L2 cache if the system has L2 cache?
2009-11-02 11:00 ` Russell King - ARM Linux
@ 2009-11-03 3:10 ` Peter Chen
0 siblings, 0 replies; 5+ messages in thread
From: Peter Chen @ 2009-11-03 3:10 UTC (permalink / raw)
To: linux-arm-kernel
Russell King - ARM Linux wrote:
> On Mon, Nov 02, 2009 at 10:32:13AM +0800, Peter Chen wrote:
>> I met a problem if the address is first used by cachable, then
>> uncachable. After that, the address will be filled with cachable value
>> after that L2 cache line is evicted.
>
> What _exactly_ are you trying to do? Why are you apparantly mapping
> something in as cacheable, and then making it uncacheable?
>
This is 3rd party released code
This problem happens at device driver wants to alloc uncachable memory,
but it doesn't alloc it using dma_ API.
--
Best regards,
Peter Chen
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2009-11-03 3:10 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2009-11-02 2:32 Why flush_cache_all() not including flushing L2 cache if the system has L2 cache? Peter Chen
2009-11-02 3:42 ` Eric Miao
2009-11-02 10:43 ` Peter Chen
2009-11-02 11:00 ` Russell King - ARM Linux
2009-11-03 3:10 ` Peter Chen
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