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From: andy@warmcat.com (Andy Green)
To: linux-arm-kernel@lists.infradead.org
Subject: "ARM: MX3: fix CPU revision number detection" breaks QONG support
Date: Mon, 14 Dec 2009 14:10:26 +0000	[thread overview]
Message-ID: <4B264752.1080709@warmcat.com> (raw)
In-Reply-To: <20091214135722.CBCBF4C026@gemini.denx.de>

On 12/14/09 13:57, Somebody in the thread at some point said:

Hi Wolfgang -

> In Linux, the kernel hangs here:
>
> 	/* read SREV register from IIM module */
> 	srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR) + MXC_IIMSREV);

In iMX31 IIM is very strangely a specifically 8-bit peripheral on a 
32-bit bus.  I wrote some code to read and write the fuses recently.

Maybe it's required to change it to __raw_readb; mine are already byte 
operations.

> In U-Boot, I can read this register just fine:
>
> 	=>  md 5001c024 1
> 	5001c024: 00000028    (...
>
> In Linux, the IO_ADDRESS() makes this a read from 0xFC11C024, which
> hangs.
>
> So if this is a clock thing, then it must be a clock being disabled by
> Linux.

Around my (working) IIM operations I have this code:

	iim_clk = clk_get(NULL, "iim");
	if (IS_ERR(iim_clk)) {
		pr_err("No IIM clock defined\n");
		return -EINVAL;
	}
	clk_enable(iim_clk);

...

	clk_disable(iim_clk);
	clk_put(iim_clk);

-Andy

  reply	other threads:[~2009-12-14 14:10 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-12-11 14:33 "ARM: MX3: fix CPU revision number detection" breaks QONG support Wolfgang Denk
2009-12-11 23:47 ` Daniel Mack
2009-12-14 13:57   ` Wolfgang Denk
2009-12-14 14:10     ` Andy Green [this message]
2009-12-14 15:04     ` Daniel Mack
2009-12-14 21:41       ` valentin.longchamp at epfl.ch
2009-12-14 22:42         ` Andy Green
2009-12-14 23:28         ` Wolfgang Denk
2009-12-14 23:27 ` [PATCH] ARM: MX3: make CPU revision number detection work on all boards Wolfgang Denk
2009-12-15  0:02   ` Daniel Mack
2009-12-15 10:37   ` Sascha Hauer

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