* Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs
@ 2010-01-17 20:05 ` Jean Delvare
0 siblings, 0 replies; 25+ messages in thread
From: Jean Delvare @ 2010-01-17 20:05 UTC (permalink / raw)
To: Robert Hancock
Cc: Yuhong Bao, yong.y.wang, linux-kernel, huaxu.wan, lm-sensors
On Sun, 17 Jan 2010 13:29:06 -0600, Robert Hancock wrote:
> On 01/17/2010 09:15 AM, Jean Delvare wrote:
> > On Fri, 15 Jan 2010 18:02:27 -0800, Yuhong Bao wrote:
> >>
> >>> No matter what chipset or gfx you use with the new Atom chip, the
> >>> integrated memory controller (IMC) will always be used. This patch
> >>> checks the presence of that IMC. Hope this clarifies.
> >> To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
> >
> > What prevents another vendor from selling a compatible south bridge
> > then?
>
> Nothing (other than licensing for the DMI bus, see NVIDIA and the
> problems this creates for their ION chipset). I'm assuming this patch is
> checking for the host bridge device though, that is integrated into the
> CPU and would always be present.
That's where I am confused. The patch checks for the presence of the
Intel NM10, which, reading its description looks much like a south
bridge and not a memory controller (north bridge). So I think the patch
is wrong (or at least incomplete).
Anyway, how difficult would it be to set TjMax based on the CPUID? I
presume that the Intel Atom 400 and 500 series have their own CPUID
value, haven't they? This would seem even easier that checking for a
PCI device.
--
Jean Delvare
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for
2010-01-17 20:05 ` [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs Jean Delvare
@ 2010-01-18 6:58 ` Yong Wang
-1 siblings, 0 replies; 25+ messages in thread
From: Yong Wang @ 2010-01-18 6:58 UTC (permalink / raw)
To: Jean Delvare
Cc: Robert Hancock, Yuhong Bao, yong.y.wang, linux-kernel, huaxu.wan,
lm-sensors
On Sun, Jan 17, 2010 at 09:05:36PM +0100, Jean Delvare wrote:
> On Sun, 17 Jan 2010 13:29:06 -0600, Robert Hancock wrote:
> > On 01/17/2010 09:15 AM, Jean Delvare wrote:
> > > On Fri, 15 Jan 2010 18:02:27 -0800, Yuhong Bao wrote:
> > >>
> > >>> No matter what chipset or gfx you use with the new Atom chip, the
> > >>> integrated memory controller (IMC) will always be used. This patch
> > >>> checks the presence of that IMC. Hope this clarifies.
> > >> To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
This is correct.
> > >
> > > What prevents another vendor from selling a compatible south bridge
> > > then?
> >
> > Nothing (other than licensing for the DMI bus, see NVIDIA and the
> > problems this creates for their ION chipset). I'm assuming this patch is
> > checking for the host bridge device though, that is integrated into the
> > CPU and would always be present.
>
> That's where I am confused. The patch checks for the presence of the
> Intel NM10, which, reading its description looks much like a south
> bridge and not a memory controller (north bridge). So I think the patch
> is wrong (or at least incomplete).
>
Sorry, I made a mistake in the patch description. The new Atom CPU is
coupled with integrated gfx and memory controller in one package. NM10
chipset is another chip. This patch does check the presence of the
integrated memory controller, i.e. 00:00.0 Host bridge device, which
will always be present no matter whether NM10 chipset is used or not.
> Anyway, how difficult would it be to set TjMax based on the CPUID? I
> presume that the Intel Atom 400 and 500 series have their own CPUID
> value, haven't they? This would seem even easier that checking for a
> PCI device.
>
CPUID value (family and model number) remains the same for all Atom CPUs
thus far. That is why we check the new Atom CPU this way.
Thanks
-Yong
_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs
@ 2010-01-18 6:58 ` Yong Wang
0 siblings, 0 replies; 25+ messages in thread
From: Yong Wang @ 2010-01-18 6:58 UTC (permalink / raw)
To: Jean Delvare
Cc: Robert Hancock, Yuhong Bao, yong.y.wang, linux-kernel, huaxu.wan,
lm-sensors
On Sun, Jan 17, 2010 at 09:05:36PM +0100, Jean Delvare wrote:
> On Sun, 17 Jan 2010 13:29:06 -0600, Robert Hancock wrote:
> > On 01/17/2010 09:15 AM, Jean Delvare wrote:
> > > On Fri, 15 Jan 2010 18:02:27 -0800, Yuhong Bao wrote:
> > >>
> > >>> No matter what chipset or gfx you use with the new Atom chip, the
> > >>> integrated memory controller (IMC) will always be used. This patch
> > >>> checks the presence of that IMC. Hope this clarifies.
> > >> To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
This is correct.
> > >
> > > What prevents another vendor from selling a compatible south bridge
> > > then?
> >
> > Nothing (other than licensing for the DMI bus, see NVIDIA and the
> > problems this creates for their ION chipset). I'm assuming this patch is
> > checking for the host bridge device though, that is integrated into the
> > CPU and would always be present.
>
> That's where I am confused. The patch checks for the presence of the
> Intel NM10, which, reading its description looks much like a south
> bridge and not a memory controller (north bridge). So I think the patch
> is wrong (or at least incomplete).
>
Sorry, I made a mistake in the patch description. The new Atom CPU is
coupled with integrated gfx and memory controller in one package. NM10
chipset is another chip. This patch does check the presence of the
integrated memory controller, i.e. 00:00.0 Host bridge device, which
will always be present no matter whether NM10 chipset is used or not.
> Anyway, how difficult would it be to set TjMax based on the CPUID? I
> presume that the Intel Atom 400 and 500 series have their own CPUID
> value, haven't they? This would seem even easier that checking for a
> PCI device.
>
CPUID value (family and model number) remains the same for all Atom CPUs
thus far. That is why we check the new Atom CPU this way.
Thanks
-Yong
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom
2010-01-18 6:58 ` [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs Yong Wang
@ 2010-01-18 8:14 ` Jean Delvare
-1 siblings, 0 replies; 25+ messages in thread
From: Jean Delvare @ 2010-01-18 8:14 UTC (permalink / raw)
To: Yong Wang; +Cc: Robert Hancock, Yuhong Bao, linux-kernel, huaxu.wan, lm-sensors
On Mon, 18 Jan 2010 14:58:21 +0800, Yong Wang wrote:
> On Sun, Jan 17, 2010 at 09:05:36PM +0100, Jean Delvare wrote:
> > That's where I am confused. The patch checks for the presence of the
> > Intel NM10, which, reading its description looks much like a south
> > bridge and not a memory controller (north bridge). So I think the patch
> > is wrong (or at least incomplete).
>
> Sorry, I made a mistake in the patch description. The new Atom CPU is
> coupled with integrated gfx and memory controller in one package. NM10
> chipset is another chip. This patch does check the presence of the
> integrated memory controller, i.e. 00:00.0 Host bridge device, which
> will always be present no matter whether NM10 chipset is used or not.
OK. Then indeed the patch description was rather bad. Even the comments
in the code are misleading, they mention the NM10 when they don't
really have to.
But at least if the code itself is OK... that's not that bad.
> > Anyway, how difficult would it be to set TjMax based on the CPUID? I
> > presume that the Intel Atom 400 and 500 series have their own CPUID
> > value, haven't they? This would seem even easier that checking for a
> > PCI device.
>
> CPUID value (family and model number) remains the same for all Atom CPUs
> thus far. That is why we check the new Atom CPU this way.
What about the stepping value? Don't these CPU models have their own?
Thanks,
--
Jean Delvare
_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs
@ 2010-01-18 8:14 ` Jean Delvare
0 siblings, 0 replies; 25+ messages in thread
From: Jean Delvare @ 2010-01-18 8:14 UTC (permalink / raw)
To: Yong Wang; +Cc: Robert Hancock, Yuhong Bao, linux-kernel, huaxu.wan, lm-sensors
On Mon, 18 Jan 2010 14:58:21 +0800, Yong Wang wrote:
> On Sun, Jan 17, 2010 at 09:05:36PM +0100, Jean Delvare wrote:
> > That's where I am confused. The patch checks for the presence of the
> > Intel NM10, which, reading its description looks much like a south
> > bridge and not a memory controller (north bridge). So I think the patch
> > is wrong (or at least incomplete).
>
> Sorry, I made a mistake in the patch description. The new Atom CPU is
> coupled with integrated gfx and memory controller in one package. NM10
> chipset is another chip. This patch does check the presence of the
> integrated memory controller, i.e. 00:00.0 Host bridge device, which
> will always be present no matter whether NM10 chipset is used or not.
OK. Then indeed the patch description was rather bad. Even the comments
in the code are misleading, they mention the NM10 when they don't
really have to.
But at least if the code itself is OK... that's not that bad.
> > Anyway, how difficult would it be to set TjMax based on the CPUID? I
> > presume that the Intel Atom 400 and 500 series have their own CPUID
> > value, haven't they? This would seem even easier that checking for a
> > PCI device.
>
> CPUID value (family and model number) remains the same for all Atom CPUs
> thus far. That is why we check the new Atom CPU this way.
What about the stepping value? Don't these CPU models have their own?
Thanks,
--
Jean Delvare
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for
2010-01-18 8:14 ` [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs Jean Delvare
@ 2010-01-18 8:27 ` Yong Wang
-1 siblings, 0 replies; 25+ messages in thread
From: Yong Wang @ 2010-01-18 8:27 UTC (permalink / raw)
To: Jean Delvare
Cc: Robert Hancock, Yuhong Bao, linux-kernel, huaxu.wan, lm-sensors
On Mon, Jan 18, 2010 at 09:14:51AM +0100, Jean Delvare wrote:
> On Mon, 18 Jan 2010 14:58:21 +0800, Yong Wang wrote:
> > On Sun, Jan 17, 2010 at 09:05:36PM +0100, Jean Delvare wrote:
> > > That's where I am confused. The patch checks for the presence of the
> > > Intel NM10, which, reading its description looks much like a south
> > > bridge and not a memory controller (north bridge). So I think the patch
> > > is wrong (or at least incomplete).
> >
> > Sorry, I made a mistake in the patch description. The new Atom CPU is
> > coupled with integrated gfx and memory controller in one package. NM10
> > chipset is another chip. This patch does check the presence of the
> > integrated memory controller, i.e. 00:00.0 Host bridge device, which
> > will always be present no matter whether NM10 chipset is used or not.
>
> OK. Then indeed the patch description was rather bad. Even the comments
> in the code are misleading, they mention the NM10 when they don't
> really have to.
>
> But at least if the code itself is OK... that's not that bad.
>
> > > Anyway, how difficult would it be to set TjMax based on the CPUID? I
> > > presume that the Intel Atom 400 and 500 series have their own CPUID
> > > value, haven't they? This would seem even easier that checking for a
> > > PCI device.
> >
> > CPUID value (family and model number) remains the same for all Atom CPUs
> > thus far. That is why we check the new Atom CPU this way.
>
> What about the stepping value? Don't these CPU models have their own?
>
The stepping value is not architectually defined. Therefore, it is not
the recommended way to detect CPU make and models.
Thanks
-Yong
_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs
@ 2010-01-18 8:27 ` Yong Wang
0 siblings, 0 replies; 25+ messages in thread
From: Yong Wang @ 2010-01-18 8:27 UTC (permalink / raw)
To: Jean Delvare
Cc: Robert Hancock, Yuhong Bao, linux-kernel, huaxu.wan, lm-sensors
On Mon, Jan 18, 2010 at 09:14:51AM +0100, Jean Delvare wrote:
> On Mon, 18 Jan 2010 14:58:21 +0800, Yong Wang wrote:
> > On Sun, Jan 17, 2010 at 09:05:36PM +0100, Jean Delvare wrote:
> > > That's where I am confused. The patch checks for the presence of the
> > > Intel NM10, which, reading its description looks much like a south
> > > bridge and not a memory controller (north bridge). So I think the patch
> > > is wrong (or at least incomplete).
> >
> > Sorry, I made a mistake in the patch description. The new Atom CPU is
> > coupled with integrated gfx and memory controller in one package. NM10
> > chipset is another chip. This patch does check the presence of the
> > integrated memory controller, i.e. 00:00.0 Host bridge device, which
> > will always be present no matter whether NM10 chipset is used or not.
>
> OK. Then indeed the patch description was rather bad. Even the comments
> in the code are misleading, they mention the NM10 when they don't
> really have to.
>
> But at least if the code itself is OK... that's not that bad.
>
> > > Anyway, how difficult would it be to set TjMax based on the CPUID? I
> > > presume that the Intel Atom 400 and 500 series have their own CPUID
> > > value, haven't they? This would seem even easier that checking for a
> > > PCI device.
> >
> > CPUID value (family and model number) remains the same for all Atom CPUs
> > thus far. That is why we check the new Atom CPU this way.
>
> What about the stepping value? Don't these CPU models have their own?
>
The stepping value is not architectually defined. Therefore, it is not
the recommended way to detect CPU make and models.
Thanks
-Yong
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom
2010-01-17 20:05 ` [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs Jean Delvare
@ 2010-01-18 7:21 ` Huaxu Wan
-1 siblings, 0 replies; 25+ messages in thread
From: Huaxu Wan @ 2010-01-18 7:21 UTC (permalink / raw)
To: Jean Delvare
Cc: Robert Hancock, huaxu.wan, Yuhong Bao, lm-sensors, linux-kernel,
yong.y.wang
On 21:05 Sun 17 Jan, Jean Delvare wrote:
> On Sun, 17 Jan 2010 13:29:06 -0600, Robert Hancock wrote:
> > On 01/17/2010 09:15 AM, Jean Delvare wrote:
> > > On Fri, 15 Jan 2010 18:02:27 -0800, Yuhong Bao wrote:
> > >>
> > >>> No matter what chipset or gfx you use with the new Atom chip, the
> > >>> integrated memory controller (IMC) will always be used. This patch
> > >>> checks the presence of that IMC. Hope this clarifies.
> > >> To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
> > >
> > > What prevents another vendor from selling a compatible south bridge
> > > then?
> >
> > Nothing (other than licensing for the DMI bus, see NVIDIA and the
> > problems this creates for their ION chipset). I'm assuming this patch is
> > checking for the host bridge device though, that is integrated into the
> > CPU and would always be present.
>
> That's where I am confused. The patch checks for the presence of the
> Intel NM10, which, reading its description looks much like a south
> bridge and not a memory controller (north bridge). So I think the patch
> is wrong (or at least incomplete).
>
> Anyway, how difficult would it be to set TjMax based on the CPUID? I
> presume that the Intel Atom 400 and 500 series have their own CPUID
> value, haven't they? This would seem even easier that checking for a
> PCI device.
Actually, all the Atom processors share the same CPUID(0x1C) and the
worse is not all of them has the same TjMax. That's a big problem.
Thanks
Huaxu
_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs
@ 2010-01-18 7:21 ` Huaxu Wan
0 siblings, 0 replies; 25+ messages in thread
From: Huaxu Wan @ 2010-01-18 7:21 UTC (permalink / raw)
To: Jean Delvare
Cc: Robert Hancock, huaxu.wan, Yuhong Bao, lm-sensors, linux-kernel,
yong.y.wang
On 21:05 Sun 17 Jan, Jean Delvare wrote:
> On Sun, 17 Jan 2010 13:29:06 -0600, Robert Hancock wrote:
> > On 01/17/2010 09:15 AM, Jean Delvare wrote:
> > > On Fri, 15 Jan 2010 18:02:27 -0800, Yuhong Bao wrote:
> > >>
> > >>> No matter what chipset or gfx you use with the new Atom chip, the
> > >>> integrated memory controller (IMC) will always be used. This patch
> > >>> checks the presence of that IMC. Hope this clarifies.
> > >> To be more precise, Pine Trail Atoms integrate the entire northbridge, including the integrated graphics and the memory controller into the CPU, and there is a DMI connection to the southbridge, which is the Intel NM10, that is NOT integrated.
> > >
> > > What prevents another vendor from selling a compatible south bridge
> > > then?
> >
> > Nothing (other than licensing for the DMI bus, see NVIDIA and the
> > problems this creates for their ION chipset). I'm assuming this patch is
> > checking for the host bridge device though, that is integrated into the
> > CPU and would always be present.
>
> That's where I am confused. The patch checks for the presence of the
> Intel NM10, which, reading its description looks much like a south
> bridge and not a memory controller (north bridge). So I think the patch
> is wrong (or at least incomplete).
>
> Anyway, how difficult would it be to set TjMax based on the CPUID? I
> presume that the Intel Atom 400 and 500 series have their own CPUID
> value, haven't they? This would seem even easier that checking for a
> PCI device.
Actually, all the Atom processors share the same CPUID(0x1C) and the
worse is not all of them has the same TjMax. That's a big problem.
Thanks
Huaxu
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom
2010-01-18 7:21 ` [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs Huaxu Wan
@ 2010-01-18 8:07 ` Jean Delvare
-1 siblings, 0 replies; 25+ messages in thread
From: Jean Delvare @ 2010-01-18 8:07 UTC (permalink / raw)
To: Huaxu Wan
Cc: Robert Hancock, Yuhong Bao, lm-sensors, linux-kernel, yong.y.wang
On Mon, 18 Jan 2010 15:21:38 +0800, Huaxu Wan wrote:
> On 21:05 Sun 17 Jan, Jean Delvare wrote:
> > Anyway, how difficult would it be to set TjMax based on the CPUID? I
> > presume that the Intel Atom 400 and 500 series have their own CPUID
> > value, haven't they? This would seem even easier that checking for a
> > PCI device.
>
> Actually, all the Atom processors share the same CPUID(0x1C) and the
> worse is not all of them has the same TjMax. That's a big problem.
0x1C is the product value. The stepping value could be different. There
could also be other identification methods based on cpuid() or rdmsr()
commands. This is done quite frequently to identify specific CPU models.
--
Jean Delvare
_______________________________________________
lm-sensors mailing list
lm-sensors@lm-sensors.org
http://lists.lm-sensors.org/mailman/listinfo/lm-sensors
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [lm-sensors] [PATCH] hwmon: (coretemp) Fix TjMax for Atom N450/D410/D510 CPUs
@ 2010-01-18 8:07 ` Jean Delvare
0 siblings, 0 replies; 25+ messages in thread
From: Jean Delvare @ 2010-01-18 8:07 UTC (permalink / raw)
To: Huaxu Wan
Cc: Robert Hancock, Yuhong Bao, lm-sensors, linux-kernel, yong.y.wang
On Mon, 18 Jan 2010 15:21:38 +0800, Huaxu Wan wrote:
> On 21:05 Sun 17 Jan, Jean Delvare wrote:
> > Anyway, how difficult would it be to set TjMax based on the CPUID? I
> > presume that the Intel Atom 400 and 500 series have their own CPUID
> > value, haven't they? This would seem even easier that checking for a
> > PCI device.
>
> Actually, all the Atom processors share the same CPUID(0x1C) and the
> worse is not all of them has the same TjMax. That's a big problem.
0x1C is the product value. The stepping value could be different. There
could also be other identification methods based on cpuid() or rdmsr()
commands. This is done quite frequently to identify specific CPU models.
--
Jean Delvare
^ permalink raw reply [flat|nested] 25+ messages in thread