Query: ARM Cortex A9: Is invalidating L1 data cache mandatory before usage

[shiraz.hashim@st.com (Shiraz HASHIM)]

Hello Santosh,

On 4/17/2010 3:37 PM, Shilimkar, Santosh wrote:
>> -----Original Message-----
>> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-kernel-
>> bounces at lists.infradead.org] On Behalf Of Shiraz HASHIM
>> Sent: Saturday, April 17, 2010 3:26 PM
>> To: linux-arm-kernel at lists.infradead.org
>> Subject: Query: ARM Cortex A9: Is invalidating L1 data cache mandatory before usage
>>
>> Hello,
>>
>> I am trying to port Linux on ARM Cortex A9 based platform and what
>> I see is that if I don't invalidate the data cache before enabling
>> and using it (in arch/arm/boot/compressed/head.S) the system crashes.
> 
> Are you enabling $L1 D in your bootloader before jumping into the kernel??

No. uboot is not enabling data cache. The first time it gets enabled is
in head.S before Linux decompression.

>> I need to do the same for second core before calling secondary_startup.
>>
>> Is it normal? Why then other platforms (cortex A9 based) are not doing
>> this. What am I missing?
>>
>> thanks for your help.

regards
Shiraz