standard property to convey device dma address width?

standard property to convey device dma address width?

[Kumar Gala]

Do we or should we have a standard property to convey that address width a device is capable of?

- k

Re: standard property to convey device dma address width?

[Mitch Bradley]

Kumar Gala wrote:
> Do we or should we have a standard property to convey that address width a device is capable of?
>   

What is the context?  When Open Firmware was first developed, the only 
bus with partial addresses was ISA.  The ISA bus binding has a "dma" 
property that describes some of the legacy DMA characteristics, but 
address width isn't one of them, for reasons that I don't remember.

I thought at the time (perhaps wishfully) that partial addresses would 
not be consideration for future buses, because

a) The transition to large-scale integration had already made logic 
gates nearly "free", so there was no motivation to skimp on address 
register bits.

b) Although packages were - and still are - pin-limited, partial address 
bus connections were not feasible because of uneven bus loading problems.

c) Address and data buses were usually multiplexed onto the same pins, 
further reducing the motivation for partial addresses.

Obviously, since you are asking the question, there is some case where 
address width could be variable.  I'd be interested to learn the details.

If I had to describe a partial address, I'd consider a property name 
like "dma-address-mask", whose value is a bitmap of implemented bits, 
corresponding to the bits in a unit address for the parent bus.  
Low-order bits might be zero if the DMA addressing hardware had 
alignment restrictions.

> - k
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RE: standard property to convey device dma address width?

[Yoder Stuart-B08248]

> -----Original Message-----
> From: Kumar Gala [mailto:galak-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org]
> Sent: Monday, August 16, 2010 11:02 AM
> To: devicetree-discuss
> Cc: Yoder Stuart-B08248
> Subject: standard property to convey device dma address width?
> 
> Do we or should we have a standard property to convey that address
> width a device is capable of?

Is this a case of where a device can only address something like
32-bits, and you want some kind of per-device property to
convey this?

Stuart

Re: standard property to convey device dma address width?

[Kumar Gala]

On Aug 17, 2010, at 3:50 PM, Yoder Stuart-B08248 wrote:

> 
> 
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org]
>> Sent: Monday, August 16, 2010 11:02 AM
>> To: devicetree-discuss
>> Cc: Yoder Stuart-B08248
>> Subject: standard property to convey device dma address width?
>> 
>> Do we or should we have a standard property to convey that address
>> width a device is capable of?
> 
> Is this a case of where a device can only address something like
> 32-bits, and you want some kind of per-device property to
> convey this?
> 
> Stuart

Exactly.  With SOC devices the address width different devices on the SOC can address may (and does) very.

- k

Re: standard property to convey device dma address width?

[Kumar Gala]

On Aug 16, 2010, at 3:17 PM, Mitch Bradley wrote:

> Kumar Gala wrote:
>> Do we or should we have a standard property to convey that address width a device is capable of?
>>  
> 
> What is the context?  When Open Firmware was first developed, the only bus with partial addresses was ISA.  The ISA bus binding has a "dma" property that describes some of the legacy DMA characteristics, but address width isn't one of them, for reasons that I don't remember.
> 
> I thought at the time (perhaps wishfully) that partial addresses would not be consideration for future buses, because
> 
> a) The transition to large-scale integration had already made logic gates nearly "free", so there was no motivation to skimp on address register bits.
> 
> b) Although packages were - and still are - pin-limited, partial address bus connections were not feasible because of uneven bus loading problems.
> 
> c) Address and data buses were usually multiplexed onto the same pins, further reducing the motivation for partial addresses.
> 
> Obviously, since you are asking the question, there is some case where address width could be variable.  I'd be interested to learn the details.
> 
> If I had to describe a partial address, I'd consider a property name like "dma-address-mask", whose value is a bitmap of implemented bits, corresponding to the bits in a unit address for the parent bus.  Low-order bits might be zero if the DMA addressing hardware had alignment restrictions.

As I said to Stuart.  On the Freescale SOCs we have different device blocks w/varying dma address capabilities.  Some are limited to 32-bits some are capable of 36-bits on the same SOC.

- k

Re: standard property to convey device dma address width?

[Scott Wood]

On Tue, 17 Aug 2010 15:55:04 -0500
Kumar Gala <galak-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org> wrote:

> As I said to Stuart.  On the Freescale SOCs we have different device
> blocks w/varying dma address capabilities.  Some are limited to 32-bits
> some are capable of 36-bits on the same SOC.

Is this something that the driver would not know about, just based on
the compatible that it is matching?

-Scott

Re: standard property to convey device dma address width?

[Mitch Bradley]

Kumar Gala wrote:
> On Aug 16, 2010, at 3:17 PM, Mitch Bradley wrote:
>
>   
>> Kumar Gala wrote:
>>     
>>> Do we or should we have a standard property to convey that address width a device is capable of?
>>>  
>>>       
>> ...
>> If I had to describe a partial address, I'd consider a property name like "dma-address-mask", whose value is a bitmap of implemented bits, corresponding to the bits in a unit address for the parent bus.  Low-order bits might be zero if the DMA addressing hardware had alignment restrictions.
>>     
>
> As I said to Stuart.  On the Freescale SOCs we have different device blocks w/varying dma address capabilities.  Some are limited to 32-bits some are capable of 36-bits on the same SOC.
>
> - k
>
>   

The closest existing property that I know of is "dma-ranges" - see 
http://playground.sun.com/1275/proposals/Closed/Accepted/410-it.txt

That's not directly applicable, as "dma-ranges" in its current form 
applies to bus bridges, describing the translation between DMA addresses 
on a child bus to DMA addresses on a parent bus.

The case in question has some general similarities, in that the limited 
devices have an implicit 32-bit "child bus" that is translated to the 
36-bit parent bus, presumably by concatenating zeros in bits 35:32.  Is 
that correct, i.e. are the high bits implicitly 0?

The dma-ranges representation doesn't assume the "zero-extend" property, 
but rather explicitly lists child-base-address,parent-base-address,size 
triples.  I wonder if that generality is justifiable in this case?

I see several obvious representations with varying degrees of generality:

a) boolean property saying "this is one of those 32-bit only devices, 
with all the implications"
b) width in bits - assumes an implicit translation rule (e.g. zero-extend)
c) bitmask - assumes implicit translation rule, capable of representing 
alignment restrictions with low-order zeros
d) something like dma-ranges - explicitly represents translation rule, 
no representation for alignment restriction

My 2 cents: Generality is often only justified when you have a good 
collection of problem instances, so you can amortize the generality over 
several specific known examples.  Otherwise you often end up 
implementing something elaborate that never gets used.

Re: standard property to convey device dma address width?

[Kumar Gala]

On Aug 17, 2010, at 4:03 PM, Scott Wood wrote:

> On Tue, 17 Aug 2010 15:55:04 -0500
> Kumar Gala <galak-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org> wrote:
> 
>> As I said to Stuart.  On the Freescale SOCs we have different device
>> blocks w/varying dma address capabilities.  Some are limited to 32-bits
>> some are capable of 36-bits on the same SOC.
> 
> Is this something that the driver would not know about, just based on
> the compatible that it is matching?
> 
> -Scott

There is some variation here that is reasonable that the same compatible could have a different width for different SOC integration.

- k