[PATCH 0/5 -v2] xl: add cpuid config file option

[PATCH 0/5 -v2] xl: add cpuid config file option

[Andre Przywara]

Hi,

as promised a respun version of my xl cpuid patches.
For more explanation see below.
Changes from v1:
- adapted the IDL part (still have no full insight on this, hope I got
    it right)
- added parser for Xen legacy cpuid syntax
- implement automatic switching between legacy and new syntax
- moved parser functions to libxl.c
- support ECX subleafs
- adapt to new coding style (bracketing on single line conditionals)
- added error checking and reporting
- more comments for better understanding
- added some new CPUID feature bit names
- fixed some bugs

There are some possible extensions I already have in mind, but I'd like
to see this one applied first.

So please review, comment (and apply ;-)!

Regards,
Andre.


--------------
xl is currently ignoring the cpuid= variable in the config file. As I
don't like the current interface xm exposes (basically because it is
complicated, unintuitive and very error prone), I implemented a new
scheme for specifying CPUID flags policy, combining QEMU's and Xen's
approach:
cpuid = "<base>,<feature_name>=[01xks]*,...
The patch includes a (preliminary) list of feature names along with
their bit positions. The value for each feature bit copies the current
meaning is Xen:
0: clear, 1: set, x: don't care/use default, k: keep from host, s: use
host but preserve across migration
The value can also be a number (either in hex or decimal), so things
like "stepping=3" can be easily specified.
To show you the advantage, I quote the example config file:
  > #cpuid=[ '1:ecx=xxxxxxxxxxx00xxxxxxxxxxxxxxxxxxx,
  > #           eax=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' ]
  > # - Unset the SSE4 features (CPUID.1[ECX][20-19])
  > # - Default behaviour for all other bits in ECX And EAX registers.
new version: cpuid = "host,sse4.1=0,sse4.2=0"
  > #   Expose to the guest multi-core cpu instead of multiple processors
  > # Example for intel, expose a 8-core processor :
  > #cpuid=['1:edx=xxx1xxxxxxxxxxxxxxxxxxxxxxxxxxxx,
  > #          ebx=xxxxxxxx00010000xxxxxxxxxxxxxxxx',
  > #     '4,0:eax=001111xxxxxxxxxxxxxxxxxxxxxxxxxx']
  > #  - CPUID.1[EDX][HT] : Enable HT
  > #  - CPUID.1[EBX] : Number of vcpus * 2
  > #  - CPUID.4,0[EAX] : Number of vcpus * 2 - 1
  > #vcpus=8
new version: cpuid = "host,htt=1,proccount=16,maxcores=15"
  > # Example for amd, expose a 5-core processor :
  > # cpuid = ['1:ebx=xxxxxxxx00001010xxxxxxxxxxxxxxxx,
  > #             edx=xxx1xxxxxxxxxxxxxxxxxxxxxxxxxxxx',
  > # '0x80000001:ecx=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1x',
  > # '0x80000008:ecx=xxxxxxxxxxxxxxxxxxxxxxxxxx001001']
  > #   - CPUID.1[EBX] : Threads per Core * Cores per Socket (2 * #vcpus)
  > #   - CPUID.1[EDX][HT] : Enable HT
  > #   - CPUID.0x80000001[CmpLegacy] : Use legacy method
  > #   - CPUID.0x80000008[ECX] : #vcpus * 2 - 1
new version: cpuid="host,htt=1,cmplegacy=1,proccount=10,nc=9"


-- 
Andre Przywara
AMD-Operating System Research Center (OSRC), Dresden, Germany