[Qemu-devel] Minor MMU fixes for PowerPC 40x emulation

[John Clark <clarkjc@runbox.com>]

Hello,

I found I had to make a few minor changes to the MMU code for the
PowerPC 40x emulation to get NetBSD to run on a virtual PowerPC 405
core with qemu-system-ppcemb. The 'tlbre' instruction was not working,
and permission checking for a TLB entry was not as strict as it should
be. Diffs are included below.

Thank you.

- John Clark

diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 3bc8a34..a8c1802 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -1172,9 +1172,9 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
         case 0x1:
         check_perms:
             /* Check from TLB entry */
-            /* XXX: there is a problem here or in the TLB fill code... */
+            /* There is no longer a need to force PAGE_EXEC permission here */
+            /* because of the tlb->attr fix in helper_4xx_tlbwe_lo() */
             ctx->prot = tlb->prot;
-            ctx->prot |= PAGE_EXEC;
             ret = check_prot(ctx->prot, rw, access_type);
             if (ret == -2)
                 env->spr[SPR_40x_ESR] = 0;
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 3e6db85..54356e8 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -3929,7 +3929,7 @@ static inline int booke_page_size_to_tlb(target_ulong page_size)
 }
 
 /* Helpers for 4xx TLB management */
-target_ulong helper_4xx_tlbre_lo (target_ulong entry)
+target_ulong helper_4xx_tlbre_hi (target_ulong entry)
 {
     ppcemb_tlb_t *tlb;
     target_ulong ret;
@@ -3939,7 +3939,7 @@ target_ulong helper_4xx_tlbre_lo (target_ulong entry)
     tlb = &env->tlb[entry].tlbe;
     ret = tlb->EPN;
     if (tlb->prot & PAGE_VALID)
-        ret |= 0x400;
+        ret |= 0x40;    /* V bit is 0x40, not 0x400 */
     size = booke_page_size_to_tlb(tlb->size);
     if (size < 0 || size > 0x7)
         size = 1;
@@ -3948,7 +3948,7 @@ target_ulong helper_4xx_tlbre_lo (target_ulong entry)
     return ret;
 }
 
-target_ulong helper_4xx_tlbre_hi (target_ulong entry)
+target_ulong helper_4xx_tlbre_lo (target_ulong entry)
 {
     ppcemb_tlb_t *tlb;
     target_ulong ret;