From: "H. Peter Anvin" <hpa@zytor.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Marcio Saito <marcio@cyclades.com>,
Jiri Slaby <jirislaby@gmail.com>,
x86@kernel.org, linux-kernel@vger.kernel.org,
Tim Pepper <lnxninja@linux.vnet.ibm.com>,
Ingo Molnar <mingo@redhat.com>, Paul Mackerras <paulus@samba.org>,
John Stultz <johnstul@us.ibm.com>,
Avantika Mathur <mathur@linux.vnet.ibm.com>,
linuxppc-dev@lists.ozlabs.org
Subject: Re: [RFC] [PATCH] allow low HZ values?
Date: Mon, 11 Oct 2010 15:47:07 -0700 [thread overview]
Message-ID: <4CB393EB.3060405@zytor.com> (raw)
In-Reply-To: <alpine.LFD.2.00.1010120032060.2909@localhost6.localdomain6>
On 10/11/2010 03:33 PM, Thomas Gleixner wrote:
> On Tue, 12 Oct 2010, Benjamin Herrenschmidt wrote:
>
>> On Mon, 2010-10-11 at 13:11 -0700, Tim Pepper wrote:
>>> I'm not necessarily wanting to open up the age old question of "what is
>>> a good HZ", but we were doing some testing on timer tick overheads for
>>> HPC applications and this came up...
>>
>> Note that this is also very useful when working on CPU prototypes
>> implemented in FPGAs and running at something like 12Mhz :-)
>
> /me hands benh 0.5$ for a FPGA upgrade
That's often not possible if the CPU cannot be mapped onto a single FPGA
(either because the core is too large, multiple cores are tested, or
because there is debugging logic is included.) The interconnects slows
things down tremendously.
-hpa
WARNING: multiple messages have this Message-ID (diff)
From: "H. Peter Anvin" <hpa@zytor.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Tim Pepper <lnxninja@linux.vnet.ibm.com>,
linux-kernel@vger.kernel.org, Ingo Molnar <mingo@redhat.com>,
x86@kernel.org, Marcio Saito <marcio@cyclades.com>,
Jiri Slaby <jirislaby@gmail.com>,
Paul Mackerras <paulus@samba.org>,
linuxppc-dev@lists.ozlabs.org, John Stultz <johnstul@us.ibm.com>,
Avantika Mathur <mathur@linux.vnet.ibm.com>
Subject: Re: [RFC] [PATCH] allow low HZ values?
Date: Mon, 11 Oct 2010 15:47:07 -0700 [thread overview]
Message-ID: <4CB393EB.3060405@zytor.com> (raw)
In-Reply-To: <alpine.LFD.2.00.1010120032060.2909@localhost6.localdomain6>
On 10/11/2010 03:33 PM, Thomas Gleixner wrote:
> On Tue, 12 Oct 2010, Benjamin Herrenschmidt wrote:
>
>> On Mon, 2010-10-11 at 13:11 -0700, Tim Pepper wrote:
>>> I'm not necessarily wanting to open up the age old question of "what is
>>> a good HZ", but we were doing some testing on timer tick overheads for
>>> HPC applications and this came up...
>>
>> Note that this is also very useful when working on CPU prototypes
>> implemented in FPGAs and running at something like 12Mhz :-)
>
> /me hands benh 0.5$ for a FPGA upgrade
That's often not possible if the CPU cannot be mapped onto a single FPGA
(either because the core is too large, multiple cores are tested, or
because there is debugging logic is included.) The interconnects slows
things down tremendously.
-hpa
next prev parent reply other threads:[~2010-10-11 23:12 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-10-11 20:11 [RFC] [PATCH] allow low HZ values? Tim Pepper
2010-10-11 20:11 ` Tim Pepper
2010-10-11 20:32 ` Thomas Gleixner
2010-10-11 20:32 ` Thomas Gleixner
2010-10-11 21:11 ` Tim Pepper
2010-10-11 21:11 ` Tim Pepper
2010-10-12 14:31 ` Andi Kleen
2010-10-12 14:31 ` Andi Kleen
2010-10-12 16:56 ` Thomas Gleixner
2010-10-12 16:56 ` Thomas Gleixner
2010-10-11 22:30 ` Benjamin Herrenschmidt
2010-10-11 22:30 ` Benjamin Herrenschmidt
2010-10-11 22:33 ` Thomas Gleixner
2010-10-11 22:33 ` Thomas Gleixner
2010-10-11 22:47 ` H. Peter Anvin [this message]
2010-10-11 22:47 ` H. Peter Anvin
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