SoC Atmel SSC stereo problem

SoC Atmel SSC stereo problem

[Patrick Ziegler]

Hi,

I have some trouble with stereo audio through the atmal ssc interface 
based on at91-ssc.c.
Unfortunately left and right channels were swapped periodically.

In my environment the codec supplies the BLCK and LRC clocks and
the SSC is configured to transmit one sample on both edges of the LRC clock.
But I guess the audio frames will always start with a frame of the left 
channel
while the LRC clock is in an undefined state.

How does normally the audio driver detect when a left and when a right 
channel
frame should be send and with which it should start ?

Thanks in advance for your help.

Regards,

Patrick

-- 

Dipl.-Inf. (FH) Patrick Ziegler

University Of Applied Sciences
Kaiserslautern

Amerikastrasse 1
D-66482 Zweibruecken
Germany

Phone:	+49 631 3724 5526
Mail:	patrick.ziegler@fh-kl.de

http://www.fh-kl.de
http://www.fh-kl.de/fachbereiche/imst/iuk-knowhow.html

Re: SoC Atmel SSC stereo problem

[Clemens Ladisch]

Patrick Ziegler wrote:
> I have some trouble with stereo audio through the atmal ssc interface
> based on at91-ssc.c.

(Merged into atmel_ssc_dai.c since about one year ago.)

> Unfortunately left and right channels were swapped periodically.
> 
> In my environment the codec supplies the BLCK and LRC clocks and
> the SSC is configured to transmit one sample on both edges of the LRC clock.
> But I guess the audio frames will always start with a frame of the left channel
> while the LRC clock is in an undefined state.

Indeed.

> How does normally the audio driver detect when a left and when a right channel
> frame should be send and with which it should start ?

The driver cannot do anything about this; the hardware must be told
to start transmitting at the falling edge.

If possible.

Is there a reason why the codec supplies LRC?


Regards,
Clemens

Re: SoC Atmel SSC stereo problem

[Patrick Ziegler]

>> I have some trouble with stereo audio through the atmal ssc interface
>> based on at91-ssc.c.
> (Merged into atmel_ssc_dai.c since about one year ago.)
>> Unfortunately left and right channels were swapped periodically.
>>
>> In my environment the codec supplies the BLCK and LRC clocks and
>> the SSC is configured to transmit one sample on both edges of the LRC clock.
>> But I guess the audio frames will always start with a frame of the left channel
>> while the LRC clock is in an undefined state.
> Indeed.
>
>> How does normally the audio driver detect when a left and when a right channel
>> frame should be send and with which it should start ?
> The driver cannot do anything about this; the hardware must be told
> to start transmitting at the falling edge.
>
> If possible.
If there is only one channel to transfer, I set the start of 
transmission on the rising edge (left justified format). But if I do 
this for two channels, both channels will be transmit on the left 
channel, this is what I would expect. Is there way to tell the hardware 
(Atmel SSC on at91rm9200) that 2 Frames shall be send after a rising 
edge with an indication that the second frame shall be send after the 
falling edge ? This is the way it should work, but of course I don't 
know if it's even possible.
> Is there a reason why the codec supplies LRC?
>
The SSC is connected to a FPGA that assigns the bus to different devices 
depending on the application. And for all applications the FPGA 
generates the clocks. Maybe this is not the best solution but I will try 
to deal with this limitation first before I try to persuade other people 
to change it.

Re: SoC Atmel SSC stereo problem

[Alex]

Patrick Ziegler <patrick.ziegler <at> fh-kl.de> writes:

> The SSC is connected to a FPGA that assigns the bus to different devices 
> depending on the application. And for all applications the FPGA 
> generates the clocks. Maybe this is not the best solution but I will try 
> to deal with this limitation first before I try to persuade other people 
> to change it.
> 

Hi Patrick,

It looks like you are running the SSC TX in slave mode, with both the SCLK (the 
i2S clock) and LRCK provided by your FPGA.  It is trickier to prevent channel 
inversion in this mode.

One possible approach is to:

(1)  test for the LRCK level with a gpio pin connected to the LRCK.  This should 
normally be the same pin assigned to TX_FRAME_SYNC.  After any USB set interface 
to the alternate setting for playback of your active device, or after any 
sampling rate change etc., you re-sync the transfer to the correct LRCK edge:

        pdca_disable(PDCA_CHANNEL_SSC_TX);

        // reset the audio buffer pointers to the start of the LEFT channel etc
        // if required

    	// re-sync SSC to LRCK
        // Wait for the next frame synchronization event
        // to avoid channel inversion.  Start with left channel - FS goes low

	while (!gpio_get_pin_value(_LRCK));
	while (gpio_get_pin_value(LRCK));	
        // exit when FS goes low

        // Enable now the transfer.
        pdca_enable(PDCA_CHANNEL_SSC_TX);

(2)  start clocking data out at any LRCK edge after a suitable delay (of 1 
SCLK).  You may need to use LRCK level change rather than any edge depending on 
the hardware timing.  The delay may also need to be adjusted depending on 
hardware timing.

(3)  clock out one sample (either left or right) per LRCK edge (or level).

Of course, if you are running the SSC in master mode, there are easier ways to 
ensure channel synchronization :-)

The above suggestion is extrapolated from my project using the AT32UC3A3 which 
has a similar (more capable) SSC as the AT91.  So it may or may not work for 
you.

Alex

Re: SoC Atmel SSC stereo problem

[Patrick Ziegler]

Hi Alex,

>> The SSC is connected to a FPGA that assigns the bus to different devices
>> depending on the application. And for all applications the FPGA
>> generates the clocks. Maybe this is not the best solution but I will try
>> to deal with this limitation first before I try to persuade other people
>> to change it.
>>
>>      
> Hi Patrick,
>
> It looks like you are running the SSC TX in slave mode, with both the SCLK (the
> i2S clock) and LRCK provided by your FPGA.  It is trickier to prevent channel
> inversion in this mode.
>
> One possible  is to:
>
> (1)  test for the LRCK level with a gpio pin connected to the LRCK.  This should
> normally be the same pin assigned to TX_FRAME_SYNC.  After any USB set interface
> to the alternate setting for playback of your active device, or after any
> sampling rate change etc., you re-sync the transfer to the correct LRCK edge:
>
>          pdca_disable(PDCA_CHANNEL_SSC_TX);
>
>          // reset the audio buffer pointers to the start of the LEFT channel etc
>          // if required
>
>      	// re-sync SSC to LRCK
>          // Wait for the next frame synchronization event
>          // to avoid channel inversion.  Start with left channel - FS goes low
>
> 	while (!gpio_get_pin_value(_LRCK));
> 	while (gpio_get_pin_value(LRCK));	
>          // exit when FS goes low
>
>          // Enable now the transfer.
>          pdca_enable(PDCA_CHANNEL_SSC_TX);
>
> (2)  start clocking data out at any LRCK edge after a suitable delay (of 1
> SCLK).  You may need to use LRCK level change rather than any edge depending on
> the hardware timing.  The delay may also need to be adjusted depending on
> hardware timing.
>
> (3)  clock out one sample (either left or right) per LRCK edge (or level).
>
> Of course, if you are running the SSC in master mode, there are easier ways to
> ensure channel synchronization :-)
>
> The above suggestion is extrapolated from my project using the AT32UC3A3 which
> has a similar (more capable) SSC as the AT91.  So it may or may not work for
> you.
>
>    

Thank you for your suggestion, I will try to adept this approach for our 
needs.

Best regards

Patrick

-- 

Dipl.-Inf. (FH) Patrick Ziegler

University Of Applied Sciences
Kaiserslautern

Amerikastrasse 1
D-66482 Zweibruecken
Germany

Phone:	+49 631 3724 5526
Mail:	patrick.ziegler@fh-kl.de

http://www.fh-kl.de
http://www.fh-kl.de/fachbereiche/imst/iuk-knowhow.html