From: Ron Rondis <ron.rondis@gmail.com>
To: linux-kernel@vger.kernel.org
Subject: 64 bit PCI BAR
Date: Thu, 04 Nov 2010 07:51:26 +0200 [thread overview]
Message-ID: <4CD249DE.1050301@gmail.com> (raw)
Hi,
The following section, from PCI spec, explain the mechanism for getting
64 bit region size.
"64-bit (memory) Base Address registers can be handled the same, except
that the second
32-bit register is considered an extension of the first; i.e., bits
32-63. Software writes
0FFFFFFFFh to both registers, reads them back, and combines the result
into a 64-bit value.
Size calculation is done on the 64-bit value."
In pci/proce.c the implementation is:
read low bar
write ~0 to low bar
read low bar
write low bar
read high bar
write ~0 to high bar
read high bar
write high bar
Can someone explain the conflict between the spec and the implementation?
Please add me to CC.
Thanks,
Ron
reply other threads:[~2010-11-04 5:51 UTC|newest]
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