i.MX patches for next

i.MX patches for next

[Sascha Hauer]

The following changes since commit 255ed73db5c48bcdda69aac642e265fde60564e5:

  imx: remove deprecated symbols as all users are gone now (2010-11-05 09:12:31 +0100)

are available in the git repository at:
  git://git.pengutronix.de/git/imx/linux-2.6.git imx-pu

Sascha Hauer (7):
      ARM i.MX51 boards: Do not use PHYS_OFFSET
      ARM i.MX irq: Compile avic irq code only on SoCs that need it
      ARM i.MX51: Make CONFIG_MXC_TZIC an invisible option
      ARM i.MX irq: Allow runtime decision between AVIC and TZIC
      ARM i.MX DMA: return gracefully on different socs
      ARM i.MX51: return gracefully on different socs
      ARM i.MX27 pm: return gracefully on different socs

 arch/arm/mach-imx/Kconfig                    |    3 +
 arch/arm/mach-imx/dma-v1.c                   |    2 +-
 arch/arm/mach-imx/pm-imx27.c                 |    3 +
 arch/arm/mach-mx3/Kconfig                    |    2 +
 arch/arm/mach-mx5/board-cpuimx51.c           |    2 +-
 arch/arm/mach-mx5/board-cpuimx51sd.c         |    2 +-
 arch/arm/mach-mx5/board-mx51_3ds.c           |    2 +-
 arch/arm/mach-mx5/cpu.c                      |    3 +
 arch/arm/plat-mxc/Kconfig                    |   11 ++--
 arch/arm/plat-mxc/Makefile                   |    3 +-
 arch/arm/plat-mxc/{irq.c => avic.c}          |    2 +
 arch/arm/plat-mxc/cpu.c                      |    3 +
 arch/arm/plat-mxc/include/mach/entry-macro.S |   66 ++++++++++++++++----------
 arch/arm/plat-mxc/include/mach/mxc.h         |    8 +++
 arch/arm/plat-mxc/tzic.c                     |    3 +
 15 files changed, 79 insertions(+), 36 deletions(-)
 rename arch/arm/plat-mxc/{irq.c => avic.c} (98%)

[PATCH 1/7] ARM i.MX51 boards: Do not use PHYS_OFFSET

[Sascha Hauer]

PHYS_OFFSET may become a variable once the runtime PHYS_OFFSET
patch is merged, so use MX51_PHYS_OFFSET for boot_params.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-mx5/board-cpuimx51.c   |    2 +-
 arch/arm/mach-mx5/board-cpuimx51sd.c |    2 +-
 arch/arm/mach-mx5/board-mx51_3ds.c   |    2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 6a9792f..1e01ec7 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -292,7 +292,7 @@ static struct sys_timer mxc_timer = {
 
 MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
 	/* Maintainer: Eric B?nard <eric@eukrea.com> */
-	.boot_params = PHYS_OFFSET + 0x100,
+	.boot_params = MX51_PHYS_OFFSET + 0x100,
 	.map_io = mx51_map_io,
 	.init_irq = mx51_init_irq,
 	.init_machine = eukrea_cpuimx51_init,
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index 4b3a611..24bbdb8 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -323,7 +323,7 @@ static struct sys_timer mxc_timer = {
 
 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
 	/* Maintainer: Eric B?nard <eric@eukrea.com> */
-	.boot_params = PHYS_OFFSET + 0x100,
+	.boot_params = MX51_PHYS_OFFSET + 0x100,
 	.map_io = mx51_map_io,
 	.init_irq = mx51_init_irq,
 	.init_machine = eukrea_cpuimx51sd_init,
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 79ce8dc..873cc1f 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -186,7 +186,7 @@ static struct sys_timer mxc_timer = {
 
 MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
 	/* Maintainer: Freescale Semiconductor, Inc. */
-	.boot_params = PHYS_OFFSET + 0x100,
+	.boot_params = MX3x_PHYS_OFFSET + 0x100,
 	.map_io = mx51_map_io,
 	.init_irq = mx51_init_irq,
 	.init_machine = mxc_board_init,
-- 
1.7.2.3

[PATCH 1/7] ARM i.MX51 boards: Do not use PHYS_OFFSET

[Uwe Kleine-König]

Hey Sascha,

On Fri, Nov 05, 2010 at 10:46:05AM +0100, Sascha Hauer wrote:
> PHYS_OFFSET may become a variable once the runtime PHYS_OFFSET
> patch is merged, so use MX51_PHYS_OFFSET for boot_params.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/mach-mx5/board-cpuimx51.c   |    2 +-
>  arch/arm/mach-mx5/board-cpuimx51sd.c |    2 +-
>  arch/arm/mach-mx5/board-mx51_3ds.c   |    2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
> index 6a9792f..1e01ec7 100644
> --- a/arch/arm/mach-mx5/board-cpuimx51.c
> +++ b/arch/arm/mach-mx5/board-cpuimx51.c
> @@ -292,7 +292,7 @@ static struct sys_timer mxc_timer = {
>  
>  MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
>  	/* Maintainer: Eric B?nard <eric@eukrea.com> */
> -	.boot_params = PHYS_OFFSET + 0x100,
> +	.boot_params = MX51_PHYS_OFFSET + 0x100,
>  	.map_io = mx51_map_io,
>  	.init_irq = mx51_init_irq,
>  	.init_machine = eukrea_cpuimx51_init,
> diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
> index 4b3a611..24bbdb8 100644
> --- a/arch/arm/mach-mx5/board-cpuimx51sd.c
> +++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
> @@ -323,7 +323,7 @@ static struct sys_timer mxc_timer = {
>  
>  MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
>  	/* Maintainer: Eric B?nard <eric@eukrea.com> */
> -	.boot_params = PHYS_OFFSET + 0x100,
> +	.boot_params = MX51_PHYS_OFFSET + 0x100,
>  	.map_io = mx51_map_io,
>  	.init_irq = mx51_init_irq,
>  	.init_machine = eukrea_cpuimx51sd_init,
> diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
> index 79ce8dc..873cc1f 100644
> --- a/arch/arm/mach-mx5/board-mx51_3ds.c
> +++ b/arch/arm/mach-mx5/board-mx51_3ds.c
> @@ -186,7 +186,7 @@ static struct sys_timer mxc_timer = {
>  
>  MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
>  	/* Maintainer: Freescale Semiconductor, Inc. */
> -	.boot_params = PHYS_OFFSET + 0x100,
> +	.boot_params = MX3x_PHYS_OFFSET + 0x100,
This looks wrong.

Uwe
-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 2/7] ARM i.MX irq: Compile avic irq code only on SoCs that need it

[Sascha Hauer]

This patch adds a Kconfig option for the avic irq controller
and lets the SoCs that need it select this option.
Also, as we have two irq controllers for i.MX, irq.c is not
appropriate anymore, so rename it to avic.c

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/Kconfig           |    3 +++
 arch/arm/mach-mx3/Kconfig           |    2 ++
 arch/arm/plat-mxc/Kconfig           |    4 ++++
 arch/arm/plat-mxc/Makefile          |    3 ++-
 arch/arm/plat-mxc/{irq.c => avic.c} |    0
 5 files changed, 11 insertions(+), 1 deletions(-)
 rename arch/arm/plat-mxc/{irq.c => avic.c} (100%)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 197f9e2..58b6114 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -7,6 +7,7 @@ config SOC_IMX1
 	select CPU_ARM920T
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
+	select MXC_AVIC
 	bool
 
 comment "MX1 platforms:"
@@ -36,6 +37,7 @@ config SOC_IMX21
 	select ARCH_MXC_AUDMUX_V1
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
+	select MXC_AVIC
 	bool
 
 config SOC_IMX27
@@ -43,6 +45,7 @@ config SOC_IMX27
 	select ARCH_MXC_AUDMUX_V1
 	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
+	select MXC_AVIC
 	bool
 
 choice
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 5000ac1..7863199 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -3,6 +3,7 @@ if ARCH_MX3
 config ARCH_MX31
 	select ARCH_HAS_RNGA
 	select ARCH_MXC_AUDMUX_V2
+	select MXC_AVIC
 	bool
 
 config ARCH_MX35
@@ -10,6 +11,7 @@ config ARCH_MX35
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_MXC_AUDMUX_V2
 	select HAVE_EPIT
+	select MXC_AVIC
 
 comment "MX3 platforms:"
 
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 64e3a64..31d07c0 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -25,6 +25,7 @@ config ARCH_MX25
 	select ARCH_MXC_IOMUX_V3
 	select HAVE_FB_IMX
 	select ARCH_MXC_AUDMUX_V2
+	select MXC_AVIC
 	help
 	  This enables support for systems based on the Freescale i.MX25 family
 
@@ -75,6 +76,9 @@ config MXC_TZIC
 	  containing this interrupt controller.
 	  Say N here only if you are really sure.
 
+config MXC_AVIC
+	bool
+
 config MXC_PWM
 	tristate "Enable PWM driver"
 	select HAVE_PWM
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 3726709..0e12591 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,10 +3,11 @@
 #
 
 # Common support
-obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
+obj-y := clock.o gpio.o time.o devices.o cpu.o system.o
 
 # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
 obj-$(CONFIG_MXC_TZIC) += tzic.o
+obj-$(CONFIG_MXC_AVIC) += avic.o
 
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/avic.c
similarity index 100%
rename from arch/arm/plat-mxc/irq.c
rename to arch/arm/plat-mxc/avic.c
-- 
1.7.2.3

[PATCH 2/7] ARM i.MX irq: Compile avic irq code only on SoCs that need it

[Paulius Zaleckas]

On 11/05/2010 11:46 AM, Sascha Hauer wrote:
> This patch adds a Kconfig option for the avic irq controller
> and lets the SoCs that need it select this option.
> Also, as we have two irq controllers for i.MX, irq.c is not
> appropriate anymore, so rename it to avic.c
>
> Signed-off-by: Sascha Hauer<s.hauer@pengutronix.de>
> ---
>   arch/arm/mach-imx/Kconfig           |    3 +++
>   arch/arm/mach-mx3/Kconfig           |    2 ++
>   arch/arm/plat-mxc/Kconfig           |    4 ++++
>   arch/arm/plat-mxc/Makefile          |    3 ++-
>   arch/arm/plat-mxc/{irq.c =>  avic.c} |    0
>   5 files changed, 11 insertions(+), 1 deletions(-)
>   rename arch/arm/plat-mxc/{irq.c =>  avic.c} (100%)
>
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 197f9e2..58b6114 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -7,6 +7,7 @@ config SOC_IMX1
>   	select CPU_ARM920T
>   	select IMX_HAVE_DMA_V1
>   	select IMX_HAVE_IOMUX_V1
> +	select MXC_AVIC
>   	bool
>
>   comment "MX1 platforms:"
> @@ -36,6 +37,7 @@ config SOC_IMX21
>   	select ARCH_MXC_AUDMUX_V1
>   	select IMX_HAVE_DMA_V1
>   	select IMX_HAVE_IOMUX_V1
> +	select MXC_AVIC
>   	bool
>
>   config SOC_IMX27
> @@ -43,6 +45,7 @@ config SOC_IMX27
>   	select ARCH_MXC_AUDMUX_V1
>   	select IMX_HAVE_DMA_V1
>   	select IMX_HAVE_IOMUX_V1
> +	select MXC_AVIC
>   	bool
>
>   choice
> diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
> index 5000ac1..7863199 100644
> --- a/arch/arm/mach-mx3/Kconfig
> +++ b/arch/arm/mach-mx3/Kconfig
> @@ -3,6 +3,7 @@ if ARCH_MX3
>   config ARCH_MX31
>   	select ARCH_HAS_RNGA
>   	select ARCH_MXC_AUDMUX_V2
> +	select MXC_AVIC
>   	bool
>
>   config ARCH_MX35
> @@ -10,6 +11,7 @@ config ARCH_MX35
>   	select ARCH_MXC_IOMUX_V3
>   	select ARCH_MXC_AUDMUX_V2
>   	select HAVE_EPIT
> +	select MXC_AVIC
>
>   comment "MX3 platforms:"
>
> diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
> index 64e3a64..31d07c0 100644
> --- a/arch/arm/plat-mxc/Kconfig
> +++ b/arch/arm/plat-mxc/Kconfig
> @@ -25,6 +25,7 @@ config ARCH_MX25
>   	select ARCH_MXC_IOMUX_V3
>   	select HAVE_FB_IMX
>   	select ARCH_MXC_AUDMUX_V2
> +	select MXC_AVIC
>   	help
>   	  This enables support for systems based on the Freescale i.MX25 family
>
> @@ -75,6 +76,9 @@ config MXC_TZIC
>   	  containing this interrupt controller.
>   	  Say N here only if you are really sure.
>
> +config MXC_AVIC
> +	bool
> +
>   config MXC_PWM
>   	tristate "Enable PWM driver"
>   	select HAVE_PWM
> diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
> index 3726709..0e12591 100644
> --- a/arch/arm/plat-mxc/Makefile
> +++ b/arch/arm/plat-mxc/Makefile
> @@ -3,10 +3,11 @@
>   #
>
>   # Common support
> -obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
> +obj-y := clock.o gpio.o time.o devices.o cpu.o system.o
>
>   # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)

it is not irq.o anymore as stated in the comment

>   obj-$(CONFIG_MXC_TZIC) += tzic.o
> +obj-$(CONFIG_MXC_AVIC) += avic.o
>
>   obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
>   obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
> diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/avic.c
> similarity index 100%
> rename from arch/arm/plat-mxc/irq.c
> rename to arch/arm/plat-mxc/avic.c

[PATCH 3/7] ARM i.MX51: Make CONFIG_MXC_TZIC an invisible option

[Sascha Hauer]

There's no point showing this option to the user. The correct
value will be selected anyway.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/plat-mxc/Kconfig |    7 +------
 1 files changed, 1 insertions(+), 6 deletions(-)

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 31d07c0..8c6cd50 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -69,12 +69,7 @@ config MXC_IRQ_PRIOR
 	  Say N here, unless you have a specialized requirement.
 
 config MXC_TZIC
-	bool "Enable TrustZone Interrupt Controller"
-	depends on ARCH_MX51
-	help
-	  This will be automatically selected for all processors
-	  containing this interrupt controller.
-	  Say N here only if you are really sure.
+	bool
 
 config MXC_AVIC
 	bool
-- 
1.7.2.3

[PATCH 4/7] ARM i.MX irq: Allow runtime decision between AVIC and TZIC

[Sascha Hauer]

As we are on a path to support more different i.MX SoCs in a single
binary we have to able to support both AVIC and TZIC in a single
binary. This patch only introduces overhead when both controllers
are needed.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/plat-mxc/avic.c                     |    2 +
 arch/arm/plat-mxc/cpu.c                      |    3 +
 arch/arm/plat-mxc/include/mach/entry-macro.S |   66 ++++++++++++++++----------
 arch/arm/plat-mxc/include/mach/mxc.h         |    8 +++
 arch/arm/plat-mxc/tzic.c                     |    3 +
 5 files changed, 57 insertions(+), 25 deletions(-)

diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 7331f2a..1cb464a 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -118,6 +118,8 @@ void __init mxc_init_irq(void __iomem *irqbase)
 	int i;
 
 	avic_base = irqbase;
+	mxc_irq_base = irqbase;
+	mxc_irq_controller_type = MXC_IRQ_TYPE_AVIC;
 
 	/* put the AVIC into the reset value with
 	 * all interrupts disabled
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
index 386e0d5..dc14a1c 100644
--- a/arch/arm/plat-mxc/cpu.c
+++ b/arch/arm/plat-mxc/cpu.c
@@ -9,3 +9,6 @@ void mxc_set_cpu_type(unsigned int type)
 	__mxc_cpu_type = type;
 }
 
+void __iomem *mxc_irq_base;
+int mxc_irq_controller_type;
+
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index aeb0869..a7dd008 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -18,40 +18,18 @@
 	.endm
 
 	.macro  get_irqnr_preamble, base, tmp
-#ifndef CONFIG_MXC_TZIC
-	ldr	\base, =avic_base
+	ldr	\base, =mxc_irq_base
 	ldr	\base, [\base]
 #ifdef CONFIG_MXC_IRQ_PRIOR
 	ldr	r4, [\base, #AVIC_NIMASK]
 #endif
-#elif defined CONFIG_MXC_TZIC
-	ldr	\base, =tzic_base
-	ldr	\base, [\base]
-#endif /* CONFIG_MXC_TZIC */
 	.endm
 
 	.macro  arch_ret_to_user, tmp1, tmp2
 	.endm
 
-	@ this macro checks which interrupt occured
-	@ and returns its number in irqnr
-	@ and returns if an interrupt occured in irqstat
-	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-#ifndef CONFIG_MXC_TZIC
-	@ Load offset & priority of the highest priority
-	@ interrupt pending from AVIC_NIVECSR
-	ldr	\irqstat, [\base, #0x40]
-	@ Shift to get the decoded IRQ number, using ASR so
-	@ 'no interrupt pending' becomes 0xffffffff
-	mov	\irqnr, \irqstat, asr #16
-	@ set zero flag if IRQ + 1 == 0
-	adds	\tmp, \irqnr, #1
-#ifdef CONFIG_MXC_IRQ_PRIOR
-	bicne	\tmp, \irqstat, #0xFFFFFFE0
-	strne	\tmp, [\base, #AVIC_NIMASK]
-	streq	r4, [\base, #AVIC_NIMASK]
-#endif
-#elif defined CONFIG_MXC_TZIC
+	.macro	tzic_get_irqnr_and_base, irqnr, irqstat, base, tmp
+
 	@ Load offset & priority of the highest priority
 	@ interrupt pending.
 	@ 0xD80 is HIPND0 register
@@ -76,6 +54,44 @@
 	mov  \irqnr, #0
 2002:
 	movs \irqnr, \irqnr
+	.endm
+
+	.macro	avic_get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+	@ Load offset & priority of the highest priority
+	@ interrupt pending from AVIC_NIVECSR
+	ldr	\irqstat, [\base, #0x40]
+	@ Shift to get the decoded IRQ number, using ASR so
+	@ 'no interrupt pending' becomes 0xffffffff
+	mov	\irqnr, \irqstat, asr #16
+	@ set zero flag if IRQ + 1 == 0
+	adds	\tmp, \irqnr, #1
+#ifdef CONFIG_MXC_IRQ_PRIOR
+	bicne	\tmp, \irqstat, #0xFFFFFFE0
+	strne	\tmp, [\base, #AVIC_NIMASK]
+	streq	r4, [\base, #AVIC_NIMASK]
+#endif
+	.endm
+
+	.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+#if defined CONFIG_MXC_TZIC && defined CONFIG_MXC_AVIC
+	ldr	\tmp, =mxc_irq_controller_type
+	ldr	\tmp, [\tmp]
+	cmp	\tmp, #MXC_IRQ_TYPE_AVIC
+	beq	3001f
+
+	tzic_get_irqnr_and_base \irqnr, \irqstat, \base, \tmp
+	b	3002f
+3001:
+	avic_get_irqnr_and_base \irqnr, \irqstat, \base, \tmp
+3002:
+
+#elif defined CONFIG_MXC_TZIC
+	tzic_get_irqnr_and_base \irqnr, \irqstat, \base, \tmp
+#elif defined CONFIG_MXC_AVIC
+	avic_get_irqnr_and_base \irqnr, \irqstat, \base, \tmp
+#else
+#error no tzic and no avic?
 #endif
 	.endm
 
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index a42c720..3432b78 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -154,4 +154,12 @@ extern struct cpu_op *(*get_cpu_op)(int *op);
 #define cpu_is_mx3()	(cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
 #define cpu_is_mx2()	(cpu_is_mx21() || cpu_is_mx27())
 
+#ifndef __ASSEMBLY__
+extern int mxc_irq_controller_type;
+extern void __iomem *mxc_irq_base;
+#endif
+
+#define MXC_IRQ_TYPE_AVIC	1
+#define MXC_IRQ_TYPE_TZIC	2
+
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 3703ab2..f2179b1 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -122,6 +122,9 @@ void __init tzic_init_irq(void __iomem *irqbase)
 	int i;
 
 	tzic_base = irqbase;
+	mxc_irq_base = irqbase;
+	mxc_irq_controller_type = MXC_IRQ_TYPE_TZIC;
+
 	/* put the TZIC into the reset value with
 	 * all interrupts disabled
 	 */
-- 
1.7.2.3

[PATCH 4/7] ARM i.MX irq: Allow runtime decision between AVIC and TZIC

[Uwe Kleine-König]

On Fri, Nov 05, 2010 at 10:46:08AM +0100, Sascha Hauer wrote:
> As we are on a path to support more different i.MX SoCs in a single
> binary we have to able to support both AVIC and TZIC in a single
> binary. This patch only introduces overhead when both controllers
> are needed.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  arch/arm/plat-mxc/avic.c                     |    2 +
>  arch/arm/plat-mxc/cpu.c                      |    3 +
>  arch/arm/plat-mxc/include/mach/entry-macro.S |   66 ++++++++++++++++----------
>  arch/arm/plat-mxc/include/mach/mxc.h         |    8 +++
>  arch/arm/plat-mxc/tzic.c                     |    3 +
>  5 files changed, 57 insertions(+), 25 deletions(-)
> 
> diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
> index 7331f2a..1cb464a 100644
> --- a/arch/arm/plat-mxc/avic.c
> +++ b/arch/arm/plat-mxc/avic.c
> @@ -118,6 +118,8 @@ void __init mxc_init_irq(void __iomem *irqbase)
>  	int i;
>  
>  	avic_base = irqbase;
Is avic_base still needed?

> +	mxc_irq_base = irqbase;
> +	mxc_irq_controller_type = MXC_IRQ_TYPE_AVIC;
>  
>  	/* put the AVIC into the reset value with
>  	 * all interrupts disabled
> diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
> index 386e0d5..dc14a1c 100644
> --- a/arch/arm/plat-mxc/cpu.c
> +++ b/arch/arm/plat-mxc/cpu.c
> @@ -9,3 +9,6 @@ void mxc_set_cpu_type(unsigned int type)
>  	__mxc_cpu_type = type;
>  }
>  
> +void __iomem *mxc_irq_base;
> +int mxc_irq_controller_type;
> +
> diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
> index aeb0869..a7dd008 100644
> --- a/arch/arm/plat-mxc/include/mach/entry-macro.S
> +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
> @@ -18,40 +18,18 @@
>  	.endm
>  
>  	.macro  get_irqnr_preamble, base, tmp
> -#ifndef CONFIG_MXC_TZIC
> -	ldr	\base, =avic_base
> +	ldr	\base, =mxc_irq_base
>  	ldr	\base, [\base]
>  #ifdef CONFIG_MXC_IRQ_PRIOR
>  	ldr	r4, [\base, #AVIC_NIMASK]
>  #endif
> -#elif defined CONFIG_MXC_TZIC
> -	ldr	\base, =tzic_base
> -	ldr	\base, [\base]
> -#endif /* CONFIG_MXC_TZIC */
>  	.endm
>  
>  	.macro  arch_ret_to_user, tmp1, tmp2
>  	.endm
>  
> -	@ this macro checks which interrupt occured
> -	@ and returns its number in irqnr
> -	@ and returns if an interrupt occured in irqstat
> -	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
> -#ifndef CONFIG_MXC_TZIC
> -	@ Load offset & priority of the highest priority
> -	@ interrupt pending from AVIC_NIVECSR
> -	ldr	\irqstat, [\base, #0x40]
> -	@ Shift to get the decoded IRQ number, using ASR so
> -	@ 'no interrupt pending' becomes 0xffffffff
> -	mov	\irqnr, \irqstat, asr #16
> -	@ set zero flag if IRQ + 1 == 0
> -	adds	\tmp, \irqnr, #1
> -#ifdef CONFIG_MXC_IRQ_PRIOR
> -	bicne	\tmp, \irqstat, #0xFFFFFFE0
> -	strne	\tmp, [\base, #AVIC_NIMASK]
> -	streq	r4, [\base, #AVIC_NIMASK]
> -#endif
> -#elif defined CONFIG_MXC_TZIC
> +	.macro	tzic_get_irqnr_and_base, irqnr, irqstat, base, tmp
> +
>  	@ Load offset & priority of the highest priority
>  	@ interrupt pending.
>  	@ 0xD80 is HIPND0 register
> @@ -76,6 +54,44 @@
>  	mov  \irqnr, #0
>  2002:
>  	movs \irqnr, \irqnr
> +	.endm
> +
> +	.macro	avic_get_irqnr_and_base, irqnr, irqstat, base, tmp
> +
> +	@ Load offset & priority of the highest priority
> +	@ interrupt pending from AVIC_NIVECSR
> +	ldr	\irqstat, [\base, #0x40]
> +	@ Shift to get the decoded IRQ number, using ASR so
> +	@ 'no interrupt pending' becomes 0xffffffff
> +	mov	\irqnr, \irqstat, asr #16
> +	@ set zero flag if IRQ + 1 == 0
> +	adds	\tmp, \irqnr, #1
> +#ifdef CONFIG_MXC_IRQ_PRIOR
> +	bicne	\tmp, \irqstat, #0xFFFFFFE0
> +	strne	\tmp, [\base, #AVIC_NIMASK]
> +	streq	r4, [\base, #AVIC_NIMASK]
> +#endif
> +	.endm
> +
> +	.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
> +#if defined CONFIG_MXC_TZIC && defined CONFIG_MXC_AVIC
> +	ldr	\tmp, =mxc_irq_controller_type
> +	ldr	\tmp, [\tmp]
> +	cmp	\tmp, #MXC_IRQ_TYPE_AVIC
> +	beq	3001f
> +
> +	tzic_get_irqnr_and_base \irqnr, \irqstat, \base, \tmp
> +	b	3002f
> +3001:
> +	avic_get_irqnr_and_base \irqnr, \irqstat, \base, \tmp
> +3002:
> +
> +#elif defined CONFIG_MXC_TZIC
> +	tzic_get_irqnr_and_base \irqnr, \irqstat, \base, \tmp
> +#elif defined CONFIG_MXC_AVIC
> +	avic_get_irqnr_and_base \irqnr, \irqstat, \base, \tmp
> +#else
> +#error no tzic and no avic?
>  #endif
>  	.endm
>  
> diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
> index a42c720..3432b78 100644
> --- a/arch/arm/plat-mxc/include/mach/mxc.h
> +++ b/arch/arm/plat-mxc/include/mach/mxc.h
> @@ -154,4 +154,12 @@ extern struct cpu_op *(*get_cpu_op)(int *op);
>  #define cpu_is_mx3()	(cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
>  #define cpu_is_mx2()	(cpu_is_mx21() || cpu_is_mx27())
>  
> +#ifndef __ASSEMBLY__
> +extern int mxc_irq_controller_type;
> +extern void __iomem *mxc_irq_base;
> +#endif
> +
> +#define MXC_IRQ_TYPE_AVIC	1
> +#define MXC_IRQ_TYPE_TZIC	2
> +
>  #endif /*  __ASM_ARCH_MXC_H__ */
> diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
> index 3703ab2..f2179b1 100644
> --- a/arch/arm/plat-mxc/tzic.c
> +++ b/arch/arm/plat-mxc/tzic.c
> @@ -122,6 +122,9 @@ void __init tzic_init_irq(void __iomem *irqbase)
>  	int i;
>  
>  	tzic_base = irqbase;
ditto for tzic_base.

Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 4/7] ARM i.MX irq: Allow runtime decision between AVIC and TZIC

[Sascha Hauer]

On Fri, Nov 05, 2010 at 11:37:33AM +0100, Uwe Kleine-K?nig wrote:
> On Fri, Nov 05, 2010 at 10:46:08AM +0100, Sascha Hauer wrote:
> > As we are on a path to support more different i.MX SoCs in a single
> > binary we have to able to support both AVIC and TZIC in a single
> > binary. This patch only introduces overhead when both controllers
> > are needed.
> > 
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> >  arch/arm/plat-mxc/avic.c                     |    2 +
> >  arch/arm/plat-mxc/cpu.c                      |    3 +
> >  arch/arm/plat-mxc/include/mach/entry-macro.S |   66 ++++++++++++++++----------
> >  arch/arm/plat-mxc/include/mach/mxc.h         |    8 +++
> >  arch/arm/plat-mxc/tzic.c                     |    3 +
> >  5 files changed, 57 insertions(+), 25 deletions(-)
> > 
> > diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
> > index 7331f2a..1cb464a 100644
> > --- a/arch/arm/plat-mxc/avic.c
> > +++ b/arch/arm/plat-mxc/avic.c
> > @@ -118,6 +118,8 @@ void __init mxc_init_irq(void __iomem *irqbase)
> >  	int i;
> >  
> >  	avic_base = irqbase;
> Is avic_base still needed?
> 
> > +++ b/arch/arm/plat-mxc/tzic.c
> > @@ -122,6 +122,9 @@ void __init tzic_init_irq(void __iomem *irqbase)
> >  	int i;
> >  
> >  	tzic_base = irqbase;
> ditto for tzic_base.

The C code uses them. I only kept them to create a minimal patch. They
can be removed in a later patch.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

[PATCH 4/7] ARM i.MX irq: Allow runtime decision between AVIC and TZIC

[Uwe Kleine-König]

Hello,

On Fri, Nov 05, 2010 at 10:46:08AM +0100, Sascha Hauer wrote:
> As we are on a path to support more different i.MX SoCs in a single
> binary we have to able to support both AVIC and TZIC in a single
> binary. This patch only introduces overhead when both controllers
> are needed.
During my lunch break I remembered this patch:

	http://article.gmane.org/gmane.linux.ports.arm.kernel/84809

With that supporting both irq controllers should be a bit nicer.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 5/7] ARM i.MX DMA: return gracefully on different socs

[Sascha Hauer]

Code called from an initcall can be maybe called for
machines it's not intended for. So check for valid
machines and return gracefully if an incompatible machine
is found.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/dma-v1.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index 3e8c47c..dcb24a9 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -818,7 +818,7 @@ static int __init imx_dma_init(void)
 		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
 	else
 #endif
-		BUG();
+		return 0;
 
 	dma_clk = clk_get(NULL, "dma");
 	clk_enable(dma_clk);
-- 
1.7.2.3

[PATCH 6/7] ARM i.MX51: return gracefully on different socs

[Sascha Hauer]

Code called from an initcall can be maybe called for
machines it's not intended for. So check for valid
machines and return gracefully if an incompatible machine
is found.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-mx5/cpu.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index eaacb6e..061ab70 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -79,6 +79,9 @@ EXPORT_SYMBOL(mx51_revision);
  */
 static int __init mx51_neon_fixup(void)
 {
+	if (!cpu_is_mx51())
+		return 0;
+
 	if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
 		elf_hwcap &= ~HWCAP_NEON;
 		pr_info("Turning off NEON support, detected broken NEON implementation\n");
-- 
1.7.2.3

[PATCH 7/7] ARM i.MX27 pm: return gracefully on different socs

[Sascha Hauer]

Code called from an initcall can be maybe called for
machines it's not intended for. So check for valid
machines and return gracefully if an incompatible machine
is found.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/pm-imx27.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index afc17ce..6bf81ce 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -39,6 +39,9 @@ static struct platform_suspend_ops mx27_suspend_ops = {
 
 static int __init mx27_pm_init(void)
 {
+	if (!cpu_is_mx27())
+		return 0;
+
 	suspend_set_ops(&mx27_suspend_ops);
 	return 0;
 }
-- 
1.7.2.3