From: Stephen Caudle <scaudle@codeaurora.org>
To: Russell King - ARM Linux <linux@arm.linux.org.uk>
Cc: dwalker@codeaurora.org, linux-arm-msm@vger.kernel.org,
adharmap@codeaurora.org, linux-kernel@vger.kernel.org,
miltonm@bga.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] [ARM] gic: Unmask private interrupts on all cores during IRQ enable
Date: Wed, 01 Dec 2010 11:36:10 -0500 [thread overview]
Message-ID: <4CF6797A.2010807@codeaurora.org> (raw)
In-Reply-To: <20101130180718.GB8521@n2100.arm.linux.org.uk>
On 11/30/2010 01:07 PM, Russell King - ARM Linux wrote:
> Sorry, missed this.
>
> If it's a private peripheral, it can only be accessed from its associated
> CPU. What that means is you don't want to enable the interrupt on other
> CPUs as the peripheral may not be present or initialized on that CPU.
Understood. But the alternative is to require all code that requests a
PPI to have to enable the IRQ on the other cores. This seems
unreasonable to me.
> So I'm nervous about this change - architecturally it feels like the
> wrong thing to do to take the PPI interrupts through the generic IRQ
> infrastructure.
What do suggest as an alternative to this solution? Creating separate
IRQ numbers for each core (per PPI) doesn't seem to scale well as the
number of cores increase.
~Stephen
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
WARNING: multiple messages have this Message-ID (diff)
From: scaudle@codeaurora.org (Stephen Caudle)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] [ARM] gic: Unmask private interrupts on all cores during IRQ enable
Date: Wed, 01 Dec 2010 11:36:10 -0500 [thread overview]
Message-ID: <4CF6797A.2010807@codeaurora.org> (raw)
In-Reply-To: <20101130180718.GB8521@n2100.arm.linux.org.uk>
On 11/30/2010 01:07 PM, Russell King - ARM Linux wrote:
> Sorry, missed this.
>
> If it's a private peripheral, it can only be accessed from its associated
> CPU. What that means is you don't want to enable the interrupt on other
> CPUs as the peripheral may not be present or initialized on that CPU.
Understood. But the alternative is to require all code that requests a
PPI to have to enable the IRQ on the other cores. This seems
unreasonable to me.
> So I'm nervous about this change - architecturally it feels like the
> wrong thing to do to take the PPI interrupts through the generic IRQ
> infrastructure.
What do suggest as an alternative to this solution? Creating separate
IRQ numbers for each core (per PPI) doesn't seem to scale well as the
number of cores increase.
~Stephen
--
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2010-12-01 16:36 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-11-03 21:46 [PATCH v2] [ARM] gic: Unmask private interrupts on all cores during IRQ enable Stephen Caudle
2010-11-03 21:46 ` Stephen Caudle
2010-11-30 15:42 ` Stephen Caudle
2010-11-30 15:42 ` Stephen Caudle
2010-11-30 18:07 ` Russell King - ARM Linux
2010-11-30 18:07 ` Russell King - ARM Linux
2010-12-01 16:36 ` Stephen Caudle [this message]
2010-12-01 16:36 ` Stephen Caudle
2010-12-01 17:14 ` Russell King - ARM Linux
2010-12-01 17:14 ` Russell King - ARM Linux
2010-12-09 16:24 ` Stephen Caudle
2010-12-09 16:24 ` Stephen Caudle
2010-12-16 14:54 ` Stephen Caudle
2010-12-16 14:54 ` Stephen Caudle
2010-12-16 15:03 ` Russell King - ARM Linux
2010-12-16 15:03 ` Russell King - ARM Linux
2010-12-16 15:08 ` Stephen Caudle
2010-12-16 15:08 ` Stephen Caudle
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