[PATCH][RFC] FPU LWP 5/5: enable LWP CPUID for HVM guests

[PATCH][RFC] FPU LWP 5/5: enable LWP CPUID for HVM guests

[Wei Huang]

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This patch enables LWP related CPUID to HVM guests.

Signed-off-by: Wei Huang <wei.huang2@amd.com>



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# HG changeset patch
# User Wei Huang <wei.huang2@amd.com>
# Date 1302812280 18000
# Branch lwp3
# Node ID 21a76fc695ee621cac5ef85b5090c7a5d5615e56
# Parent  ee8656e10937121d2780862351a245ed874273fa
libxc: enable LWP CPUID for HVM guests

This patch enables LWP related CPUID to HVM guests.

Signed-off-by: Wei Huang <wei.huang2@amd.com>

diff -r ee8656e10937 -r 21a76fc695ee tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c	Thu Apr 14 15:17:18 2011 -0500
+++ b/tools/libxc/xc_cpuid_x86.c	Thu Apr 14 15:18:00 2011 -0500
@@ -31,7 +31,7 @@
 
 #define DEF_MAX_BASE 0x0000000du
 #define DEF_MAX_INTELEXT  0x80000008u
-#define DEF_MAX_AMDEXT    0x8000000au
+#define DEF_MAX_AMDEXT    0x8000001cu
 
 static int hypervisor_is_64bit(xc_interface *xch)
 {
@@ -111,7 +111,8 @@
                     bitmaskof(X86_FEATURE_3DNOWPREFETCH) |
                     bitmaskof(X86_FEATURE_XOP) |
                     bitmaskof(X86_FEATURE_FMA4) |
-                    bitmaskof(X86_FEATURE_TBM));
+                    bitmaskof(X86_FEATURE_TBM) |
+                    bitmaskof(X86_FEATURE_LWP));
         regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */
                     (is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
                     (is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) |
@@ -385,6 +386,7 @@
     case 0x80000005: /* AMD L1 cache/TLB info (dumped by Intel policy) */
     case 0x80000006: /* AMD L2/3 cache/TLB info ; Intel L2 cache features */
     case 0x8000000a: /* AMD SVM feature bits */
+    case 0x8000001c: /* AMD lightweight profiling */
         break;
 
     default:

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