Re: [Qemu-devel] [RFC] Memory API

[Avi Kivity <avi@redhat.com>]

On 05/18/2011 07:33 PM, Anthony Liguori wrote:
> On 05/18/2011 10:23 AM, Avi Kivity wrote:
>>> The tricky part is wiring this up efficiently for TCG, ie. in QEMU's
>>> softmmu. I played with passing the issuing CPUState (or NULL for
>>> devices) down the MMIO handler chain. Not totally beautiful as
>>> decentralized dispatching was still required, but at least only
>>> moderately invasive. Maybe your API allows for cleaning up the
>>> management and dispatching part, need to rethink...
>>
>> My suggestion is opposite - have a different MemoryRegion for each (e.g.
>> CPUState::memory). Then the TLBs will resolve to a different ram_addr_t
>> for the same physical address, for the local APIC range.
>
> I don't understand the different ram_addr_t part.
>

The TLBs map a virtual address to a ram_addr_t.

> The TLB should dispatch to a per-CPU dispatch table.  The per-CPU 
> should dispatch almost everything to a global dispatch table.
>
> The global dispatch table is the chipset (Northbridge/Southbridge).
>
> The chipset can then dispatch to individual busses which can then 
> further dispatch as appropriate.
>
> Overlapping regions can be handled differently at each level.  For 
> instance, if a PCI device registers an IO region to the same location 
> as the APIC, the APIC always wins because the PCI bus will never see 
> the access.
>

That's inefficient, since you always have to traverse the hierarchy.

> You cannot do this properly with a single dispatch table because the 
> behavior depends on where in the hierarchy the I/O is being handled.

You can.  When you have a TLB miss, you walk the memory hierarchy (which 
is per-cpu) and end up with a ram_addr_t which is stowed in the TLB 
entry.  Further accesses dispatch via this ram_addr_t, without taking 
the cpu into consideration (the TLB is, after all, already per-cpu).

Since each APIC will have its own ram_addr_t, we don't need per-cpu 
dispatch.

-- 
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