From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 0/5] ARMv6 and ARMv7 mm fixes
Date: Tue, 24 May 2011 14:59:53 -0700 [thread overview]
Message-ID: <4DDC2A59.8030109@codeaurora.org> (raw)
In-Reply-To: <1305890399-29075-1-git-send-email-will.deacon@arm.com>
On 05/20/2011 04:19 AM, Will Deacon wrote:
> Hello,
>
> There are a few issues with ASID handling and cache flushing on v6/v7
> CPUs that have been identified when running Linux on the Cortex-A15.
>
> These patches solve the problems for the classic page tables. Additional
> LPAE changes will be posted separately.
>
> Tested on a Realview-PBX platform with a dual-core Cortex-A9.
Should these patches be sent to the stable tree? Or do the problems only
manifest on Cortex-A15?
--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2011-05-24 21:59 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-05-20 11:19 [PATCH 0/5] ARMv6 and ARMv7 mm fixes Will Deacon
2011-05-20 11:19 ` [PATCH 1/5] ARM: cache: ensure MVA is cacheline aligned in flush_kern_dcache_area Will Deacon
2011-05-20 11:19 ` [PATCH 2/5] ARM: mm: make TTBR1 always point to swapper_pg_dir on ARMv6/7 Will Deacon
2011-05-20 11:19 ` [PATCH 3/5] ARM: mm: use TTBR1 instead of reserved context ID Will Deacon
2011-05-20 11:19 ` [PATCH 4/5] ARM: mm: fix racy ASID rollover broadcast on SMP platforms Will Deacon
2011-05-20 11:19 ` [PATCH 5/5] ARM: mm: allow ASID 0 to be allocated to tasks Will Deacon
2011-05-24 21:59 ` Stephen Boyd [this message]
2011-05-25 12:50 ` [PATCH 0/5] ARMv6 and ARMv7 mm fixes Will Deacon
2011-05-25 18:11 ` Stephen Boyd
2011-05-25 20:52 ` Russell King - ARM Linux
2011-05-26 10:15 ` Will Deacon
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