From: robherring2@gmail.com (Rob Herring)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] ARM: l2x0: Add OF based initialization
Date: Wed, 01 Jun 2011 14:01:03 -0500 [thread overview]
Message-ID: <4DE68C6F.4000904@gmail.com> (raw)
In-Reply-To: <BANLkTik86CVS0cWOnapnh7dn5F1EOCsmVw@mail.gmail.com>
On 06/01/2011 01:40 PM, Olof Johansson wrote:
> On Wed, Jun 1, 2011 at 9:37 AM, Rob Herring<robherring2@gmail.com> wrote:
>> From: Rob Herring<rob.herring@calxeda.com>
>>
>> This adds probing for pl310 cache controller via device tree. An example
>> binding looks like this:
>>
>> L2: l2-cache {
>> compatible = "arm,pl310-cache", "cache";
>
> "cache" is too generic to be useful. "arm,pl2x0-cache" would be a more
> meaningful fallback, I think?
I agree. This is what ePAPR says should be present for caches along with
a more specific string.
Based on the prior discussion on pmu naming, it should be the specific
model. There is no such thing as a pl2x0. The models of L2 controllers
the cache-l2x0.c code supports are:
PL310
L220
L210
And my compatible strings reflect that.
>
> (Same comment as for 1/3: The bindings need to be documented. Same
> applies to 2/3, obviousy).
>
Will do.
Rob
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>
Cc: devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH 3/3] ARM: l2x0: Add OF based initialization
Date: Wed, 01 Jun 2011 14:01:03 -0500 [thread overview]
Message-ID: <4DE68C6F.4000904@gmail.com> (raw)
In-Reply-To: <BANLkTik86CVS0cWOnapnh7dn5F1EOCsmVw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 06/01/2011 01:40 PM, Olof Johansson wrote:
> On Wed, Jun 1, 2011 at 9:37 AM, Rob Herring<robherring2-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> From: Rob Herring<rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org>
>>
>> This adds probing for pl310 cache controller via device tree. An example
>> binding looks like this:
>>
>> L2: l2-cache {
>> compatible = "arm,pl310-cache", "cache";
>
> "cache" is too generic to be useful. "arm,pl2x0-cache" would be a more
> meaningful fallback, I think?
I agree. This is what ePAPR says should be present for caches along with
a more specific string.
Based on the prior discussion on pmu naming, it should be the specific
model. There is no such thing as a pl2x0. The models of L2 controllers
the cache-l2x0.c code supports are:
PL310
L220
L210
And my compatible strings reflect that.
>
> (Same comment as for 1/3: The bindings need to be documented. Same
> applies to 2/3, obviousy).
>
Will do.
Rob
next prev parent reply other threads:[~2011-06-01 19:01 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-01 16:37 [PATCH 0/3] DT bindings Cortex A9 peripherals Rob Herring
2011-06-01 16:37 ` Rob Herring
2011-06-01 16:37 ` [PATCH 1/3] ARM: pmu: add OF probing support Rob Herring
2011-06-01 16:37 ` Rob Herring
2011-06-01 18:37 ` Olof Johansson
2011-06-01 18:37 ` Olof Johansson
2011-06-01 16:37 ` [PATCH 2/3] ARM: gic: add OF based initialization Rob Herring
2011-06-01 16:37 ` Rob Herring
2011-06-01 16:37 ` [PATCH 3/3] ARM: l2x0: Add " Rob Herring
2011-06-01 16:37 ` Rob Herring
2011-06-01 18:40 ` Olof Johansson
2011-06-01 18:40 ` Olof Johansson
2011-06-01 19:01 ` Rob Herring [this message]
2011-06-01 19:01 ` Rob Herring
-- strict thread matches above, loose matches on Subject: below --
2011-06-07 14:22 [PATCH v2 0/3] DT bindings for Cortex A9 peripherals Rob Herring
2011-06-07 14:22 ` [PATCH 3/3] ARM: l2x0: Add OF based initialization Rob Herring
2011-06-07 14:22 ` Rob Herring
2011-06-07 16:20 ` Olof Johansson
2011-06-07 16:20 ` Olof Johansson
2011-06-07 16:54 ` Rob Herring
2011-06-07 16:54 ` Rob Herring
2011-06-07 18:49 ` Olof Johansson
2011-06-07 18:49 ` Olof Johansson
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