IVB page flipping fixes (hopefully final)

IVB page flipping fixes (hopefully final)

[Jesse Barnes]

This set addresses comments from Dan and Chris, namely:
  - pin & fence the new fb on the correct ring for IVB
  - cleanup gen2/3 wait code by putting it in gen2/3 wait functions
  - remove dead code
  - fix a race in the split code with the interrupt handler and flip pending

Thanks,
Jesse

[PATCH 1/2] drm/i915: split page flip queueing into per-chipset functions

[Jesse Barnes]

This makes things a little clearer and prevents us from running old code
on a new chipset that may not be supported.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.h      |    3 +
 drivers/gpu/drm/i915/intel_display.c |  269 +++++++++++++++++++++++-----------
 2 files changed, 189 insertions(+), 83 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f63ee16..eddabf6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -211,6 +211,9 @@ struct drm_i915_display_funcs {
 	void (*fdi_link_train)(struct drm_crtc *crtc);
 	void (*init_clock_gating)(struct drm_device *dev);
 	void (*init_pch_clock_gating)(struct drm_device *dev);
+	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
+			  struct drm_framebuffer *fb,
+			  struct drm_i915_gem_object *obj);
 	/* clock updates for mode set */
 	/* cursor updates */
 	/* render clock increase/decrease */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 81a9059..37e74e9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6262,6 +6262,164 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
 	spin_unlock_irqrestore(&dev->event_lock, flags);
 }
 
+static int intel_gen2_queue_flip(struct drm_device *dev,
+				 struct drm_crtc *crtc,
+				 struct drm_framebuffer *fb,
+				 struct drm_i915_gem_object *obj)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	unsigned long offset;
+	u32 flip_mask;
+	int ret;
+
+	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
+	if (ret)
+		goto out;
+
+	/* Offset into the new buffer for cases of shared fbs between CRTCs */
+	offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
+
+	ret = BEGIN_LP_RING(6);
+	if (ret)
+		goto out;
+
+	/* Can't queue multiple flips, so wait for the previous
+	 * one to finish before executing the next.
+	 */
+	if (intel_crtc->plane)
+		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
+	else
+		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
+	OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
+	OUT_RING(MI_NOOP);
+	OUT_RING(MI_DISPLAY_FLIP |
+		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+	OUT_RING(fb->pitch);
+	OUT_RING(obj->gtt_offset + offset);
+	OUT_RING(MI_NOOP);
+	ADVANCE_LP_RING();
+out:
+	return ret;
+}
+
+static int intel_gen3_queue_flip(struct drm_device *dev,
+				 struct drm_crtc *crtc,
+				 struct drm_framebuffer *fb,
+				 struct drm_i915_gem_object *obj)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	unsigned long offset;
+	u32 flip_mask;
+	int ret;
+
+	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
+	if (ret)
+		goto out;
+
+	/* Offset into the new buffer for cases of shared fbs between CRTCs */
+	offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
+
+	ret = BEGIN_LP_RING(6);
+	if (ret)
+		goto out;
+
+	if (intel_crtc->plane)
+		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
+	else
+		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
+	OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
+	OUT_RING(MI_NOOP);
+	OUT_RING(MI_DISPLAY_FLIP_I915 |
+		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+	OUT_RING(fb->pitch);
+	OUT_RING(obj->gtt_offset + offset);
+	OUT_RING(MI_NOOP);
+
+	ADVANCE_LP_RING();
+out:
+	return ret;
+}
+
+static int intel_gen4_queue_flip(struct drm_device *dev,
+				 struct drm_crtc *crtc,
+				 struct drm_framebuffer *fb,
+				 struct drm_i915_gem_object *obj)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	uint32_t pf, pipesrc;
+	int ret;
+
+	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
+	if (ret)
+		goto out;
+
+	ret = BEGIN_LP_RING(4);
+	if (ret)
+		goto out;
+
+	/* i965+ uses the linear or tiled offsets from the
+	 * Display Registers (which do not change across a page-flip)
+	 * so we need only reprogram the base address.
+	 */
+	OUT_RING(MI_DISPLAY_FLIP |
+		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+	OUT_RING(fb->pitch);
+	OUT_RING(obj->gtt_offset | obj->tiling_mode);
+
+	/* XXX Enabling the panel-fitter across page-flip is so far
+	 * untested on non-native modes, so ignore it for now.
+	 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
+	 */
+	pf = 0;
+	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
+	OUT_RING(pf | pipesrc);
+	ADVANCE_LP_RING();
+out:
+	return ret;
+}
+
+static int intel_gen6_queue_flip(struct drm_device *dev,
+				 struct drm_crtc *crtc,
+				 struct drm_framebuffer *fb,
+				 struct drm_i915_gem_object *obj)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	uint32_t pf, pipesrc;
+	int ret;
+
+	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
+	if (ret)
+		goto out;
+
+	ret = BEGIN_LP_RING(4);
+	if (ret)
+		goto out;
+
+	OUT_RING(MI_DISPLAY_FLIP |
+		 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+	OUT_RING(fb->pitch | obj->tiling_mode);
+	OUT_RING(obj->gtt_offset);
+
+	pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
+	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
+	OUT_RING(pf | pipesrc);
+	ADVANCE_LP_RING();
+out:
+	return ret;
+}
+
+static int intel_default_queue_flip(struct drm_device *dev,
+				    struct drm_crtc *crtc,
+				    struct drm_framebuffer *fb,
+				    struct drm_i915_gem_object *obj)
+{
+	return -ENODEV;
+}
+
 static int intel_crtc_page_flip(struct drm_crtc *crtc,
 				struct drm_framebuffer *fb,
 				struct drm_pending_vblank_event *event)
@@ -6272,9 +6430,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 	struct drm_i915_gem_object *obj;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_unpin_work *work;
-	unsigned long flags, offset;
-	int pipe = intel_crtc->pipe;
-	u32 pf, pipesrc;
+	unsigned long flags;
 	int ret;
 
 	work = kzalloc(sizeof *work, GFP_KERNEL);
@@ -6303,9 +6459,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 	obj = intel_fb->obj;
 
 	mutex_lock(&dev->struct_mutex);
-	ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
-	if (ret)
-		goto cleanup_work;
 
 	/* Reference the objects for the scheduled work. */
 	drm_gem_object_reference(&work->old_fb_obj->base);
@@ -6317,91 +6470,18 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 	if (ret)
 		goto cleanup_objs;
 
-	if (IS_GEN3(dev) || IS_GEN2(dev)) {
-		u32 flip_mask;
-
-		/* Can't queue multiple flips, so wait for the previous
-		 * one to finish before executing the next.
-		 */
-		ret = BEGIN_LP_RING(2);
-		if (ret)
-			goto cleanup_objs;
-
-		if (intel_crtc->plane)
-			flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
-		else
-			flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
-		OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
-		OUT_RING(MI_NOOP);
-		ADVANCE_LP_RING();
-	}
-
 	work->pending_flip_obj = obj;
 
 	work->enable_stall_check = true;
 
-	/* Offset into the new buffer for cases of shared fbs between CRTCs */
-	offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
-
-	ret = BEGIN_LP_RING(4);
-	if (ret)
-		goto cleanup_objs;
-
 	/* Block clients from rendering to the new back buffer until
 	 * the flip occurs and the object is no longer visible.
 	 */
 	atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
 
-	switch (INTEL_INFO(dev)->gen) {
-	case 2:
-		OUT_RING(MI_DISPLAY_FLIP |
-			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-		OUT_RING(fb->pitch);
-		OUT_RING(obj->gtt_offset + offset);
-		OUT_RING(MI_NOOP);
-		break;
-
-	case 3:
-		OUT_RING(MI_DISPLAY_FLIP_I915 |
-			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-		OUT_RING(fb->pitch);
-		OUT_RING(obj->gtt_offset + offset);
-		OUT_RING(MI_NOOP);
-		break;
-
-	case 4:
-	case 5:
-		/* i965+ uses the linear or tiled offsets from the
-		 * Display Registers (which do not change across a page-flip)
-		 * so we need only reprogram the base address.
-		 */
-		OUT_RING(MI_DISPLAY_FLIP |
-			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-		OUT_RING(fb->pitch);
-		OUT_RING(obj->gtt_offset | obj->tiling_mode);
-
-		/* XXX Enabling the panel-fitter across page-flip is so far
-		 * untested on non-native modes, so ignore it for now.
-		 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
-		 */
-		pf = 0;
-		pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
-		OUT_RING(pf | pipesrc);
-		break;
-
-	case 6:
-	case 7:
-		OUT_RING(MI_DISPLAY_FLIP |
-			 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-		OUT_RING(fb->pitch | obj->tiling_mode);
-		OUT_RING(obj->gtt_offset);
-
-		pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
-		pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
-		OUT_RING(pf | pipesrc);
-		break;
-	}
-	ADVANCE_LP_RING();
+	ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
+	if (ret)
+		goto cleanup_pending;
 
 	mutex_unlock(&dev->struct_mutex);
 
@@ -6409,10 +6489,11 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
 	return 0;
 
+cleanup_pending:
+	atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
 cleanup_objs:
 	drm_gem_object_unreference(&work->old_fb_obj->base);
 	drm_gem_object_unreference(&obj->base);
-cleanup_work:
 	mutex_unlock(&dev->struct_mutex);
 
 	spin_lock_irqsave(&dev->event_lock, flags);
@@ -7657,6 +7738,28 @@ static void intel_init_display(struct drm_device *dev)
 		else
 			dev_priv->display.get_fifo_size = i830_get_fifo_size;
 	}
+
+	/* Default just returns -ENODEV to indicate unsupported */
+	dev_priv->display.queue_flip = intel_default_queue_flip;
+
+	switch (INTEL_INFO(dev)->gen) {
+	case 2:
+		dev_priv->display.queue_flip = intel_gen2_queue_flip;
+		break;
+
+	case 3:
+		dev_priv->display.queue_flip = intel_gen3_queue_flip;
+		break;
+
+	case 4:
+	case 5:
+		dev_priv->display.queue_flip = intel_gen4_queue_flip;
+		break;
+
+	case 6:
+		dev_priv->display.queue_flip = intel_gen6_queue_flip;
+		break;
+	}
 }
 
 /*
-- 
1.7.4.1

Re: [PATCH 1/2] drm/i915: split page flip queueing into per-chipset functions

[Ben Widawsky]

On Thu, Jun 16, 2011 at 09:19:13AM -0700, Jesse Barnes wrote:
> This makes things a little clearer and prevents us from running old code
> on a new chipset that may not be supported.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewied-by: Ben Widawsky <ben@bwidawsk.net>

[PATCH 2/2] drm/i915: add Ivy Bridge page flip support

[Jesse Barnes]

Use the blit ring for submitting flips since the render ring doesn't
generate flip complete interrupts.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 37e74e9..e842ed9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6412,6 +6412,33 @@ out:
 	return ret;
 }
 
+static int intel_gen7_queue_flip(struct drm_device *dev,
+				 struct drm_crtc *crtc,
+				 struct drm_framebuffer *fb,
+				 struct drm_i915_gem_object *obj)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
+	int ret;
+
+	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
+	if (ret)
+		goto out;
+
+	ret = intel_ring_begin(ring, 4);
+	if (ret)
+		goto out;
+
+	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
+	intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
+	intel_ring_emit(ring, (obj->gtt_offset));
+	intel_ring_emit(ring, (MI_NOOP));
+	intel_ring_advance(ring);
+out:
+	return ret;
+}
+
 static int intel_default_queue_flip(struct drm_device *dev,
 				    struct drm_crtc *crtc,
 				    struct drm_framebuffer *fb,
@@ -7759,6 +7786,9 @@ static void intel_init_display(struct drm_device *dev)
 	case 6:
 		dev_priv->display.queue_flip = intel_gen6_queue_flip;
 		break;
+	case 7:
+		dev_priv->display.queue_flip = intel_gen7_queue_flip;
+		break;
 	}
 }
 
-- 
1.7.4.1

Re: [PATCH 2/2] drm/i915: add Ivy Bridge page flip support

[Ben Widawsky]

On Thu, Jun 16, 2011 at 09:19:14AM -0700, Jesse Barnes wrote:
> Use the blit ring for submitting flips since the render ring doesn't
> generate flip complete interrupts.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   30 ++++++++++++++++++++++++++++++
>  1 files changed, 30 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 37e74e9..e842ed9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6412,6 +6412,33 @@ out:
>  	return ret;
>  }
>  
> +static int intel_gen7_queue_flip(struct drm_device *dev,
> +				 struct drm_crtc *crtc,
> +				 struct drm_framebuffer *fb,
> +				 struct drm_i915_gem_object *obj)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Could you put the bit about why you chose the blitter ring here.
> +	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];


Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

Re: [PATCH 2/2] drm/i915: add Ivy Bridge page flip support

[Jesse Barnes]

On Thu, 16 Jun 2011 11:54:50 -0700
Ben Widawsky <ben@bwidawsk.net> wrote:

> On Thu, Jun 16, 2011 at 09:19:14AM -0700, Jesse Barnes wrote:
> > Use the blit ring for submitting flips since the render ring doesn't
> > generate flip complete interrupts.
> > 
> > Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |   30 ++++++++++++++++++++++++++++++
> >  1 files changed, 30 insertions(+), 0 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 37e74e9..e842ed9 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6412,6 +6412,33 @@ out:
> >  	return ret;
> >  }
> >  
> > +static int intel_gen7_queue_flip(struct drm_device *dev,
> > +				 struct drm_crtc *crtc,
> > +				 struct drm_framebuffer *fb,
> > +				 struct drm_i915_gem_object *obj)
> > +{
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> Could you put the bit about why you chose the blitter ring here.
> > +	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];

Oh yeah, good call.  Will update with comments.

-- 
Jesse Barnes, Intel Open Source Technology Center

Re: [PATCH 2/2] drm/i915: add Ivy Bridge page flip support

[Jesse Barnes]

Updated with comment.

-- 
Jesse Barnes, Intel Open Source Technology Center

>From 41bdb7457beb023faa0d465f483ab793ba8896e1 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes@virtuousgeek.org>
Date: Tue, 14 Jun 2011 11:08:03 -0700
Subject: [PATCH] drm/i915: add Ivy Bridge page flip support

Use the blit ring for submitting flips since the render ring doesn't
generate flip complete interrupts.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_display.c |   36 ++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 37e74e9..9446f4e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6412,6 +6412,39 @@ out:
 	return ret;
 }
 
+/*
+ * On gen7 we currently use the blit ring because (in early silicon at least)
+ * the render ring doesn't give us interrpts for page flip completion, which
+ * means clients will hang after the first flip is queued.  Fortunately the
+ * blit ring generates interrupts properly, so use it instead.
+ */
+static int intel_gen7_queue_flip(struct drm_device *dev,
+				 struct drm_crtc *crtc,
+				 struct drm_framebuffer *fb,
+				 struct drm_i915_gem_object *obj)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
+	int ret;
+
+	ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
+	if (ret)
+		goto out;
+
+	ret = intel_ring_begin(ring, 4);
+	if (ret)
+		goto out;
+
+	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
+	intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
+	intel_ring_emit(ring, (obj->gtt_offset));
+	intel_ring_emit(ring, (MI_NOOP));
+	intel_ring_advance(ring);
+out:
+	return ret;
+}
+
 static int intel_default_queue_flip(struct drm_device *dev,
 				    struct drm_crtc *crtc,
 				    struct drm_framebuffer *fb,
@@ -7759,6 +7792,9 @@ static void intel_init_display(struct drm_device *dev)
 	case 6:
 		dev_priv->display.queue_flip = intel_gen6_queue_flip;
 		break;
+	case 7:
+		dev_priv->display.queue_flip = intel_gen7_queue_flip;
+		break;
 	}
 }
 
-- 
1.7.4.1

Re: [PATCH 2/2] drm/i915: add Ivy Bridge page flip support

[Paul Menzel]

[-- Attachment #1.1: Type: text/plain, Size: 1359 bytes --]

Am Donnerstag, den 16.06.2011, 12:18 -0700 schrieb Jesse Barnes:
> Updated with comment.
> 
> -- 
> Jesse Barnes, Intel Open Source Technology Center
> 
> >From 41bdb7457beb023faa0d465f483ab793ba8896e1 Mon Sep 17 00:00:00 2001
> From: Jesse Barnes <jbarnes@virtuousgeek.org>
> Date: Tue, 14 Jun 2011 11:08:03 -0700
> Subject: [PATCH] drm/i915: add Ivy Bridge page flip support
> 
> Use the blit ring for submitting flips since the render ring doesn't
> generate flip complete interrupts.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   36 ++++++++++++++++++++++++++++++++++
>  1 files changed, 36 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 37e74e9..9446f4e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6412,6 +6412,39 @@ out:
>  	return ret;
>  }
>  
> +/*
> + * On gen7 we currently use the blit ring because (in early silicon at least)
> + * the render ring doesn't give us interrpts for page flip completion, which

inter*u*pts

> + * means clients will hang after the first flip is queued.  Fortunately the
> + * blit ring generates interrupts properly, so use it instead.
> + */

[…]


Thanks,

Paul

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Re: IVB page flipping fixes (hopefully final)

[Daniel Vetter]

For both:
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-- 
Daniel Vetter
daniel.vetter@ffwll.ch - +41 (0) 79 364 57 48 - http://blog.ffwll.ch

Re: IVB page flipping fixes (hopefully final)

[Kenneth Graunke]

On 06/16/2011 09:19 AM, Jesse Barnes wrote:
> This set addresses comments from Dan and Chris, namely:
>    - pin&  fence the new fb on the correct ring for IVB
>    - cleanup gen2/3 wait code by putting it in gen2/3 wait functions
>    - remove dead code
>    - fix a race in the split code with the interrupt handler and flip pending
>
> Thanks,
> Jesse

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

Re: IVB page flipping fixes (hopefully final)

[Zhao, Jian J]

Hi Jesse, 
 With your these two patches: http://lists.freedesktop.org/archives/intel-gfx/2011-June/011014.html It indeed fixed three bugs(#38362, #38392, #38393) on IvyBridge, but it also caused a regression(bug #38428) and another issue is with the patched kernel, the piglit cases' passrate dropped a lot, it changed from 2372(400)/3020 to 1682(397)/3020. The format is PASS(Not Supported)/Total. Though I find some crashed cases can't be reproduced when tested separately now. I will have an investigate on it. It is better if you could have some idea of the relation between the patch and piglit tests. Thanks. 

Best regards
zhaojian  

> -----Original Message-----
> From: intel-gfx-bounces+jian.j.zhao=intel.com@lists.freedesktop.org
> [mailto:intel-gfx-bounces+jian.j.zhao=intel.com@lists.freedesktop.org] On
> Behalf Of Jesse Barnes
> Sent: Friday, June 17, 2011 12:19 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] IVB page flipping fixes (hopefully final)
> 
> This set addresses comments from Dan and Chris, namely:
>   - pin & fence the new fb on the correct ring for IVB
>   - cleanup gen2/3 wait code by putting it in gen2/3 wait functions
>   - remove dead code
>   - fix a race in the split code with the interrupt handler and flip pending
> 
> Thanks,
> Jesse
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: IVB page flipping fixes (hopefully final)

[Zhao, Jian J]

The issue(the patch may bring regression to piglit test) can't be reproduced now both with new code and old code, so maybe we can make the patch into our kernel tree. 
The details:  
I did some retest with newer commit in Mesa master and Xserver in 1.10 branch and run the piglit test without glean cases(because it will cost a long time, about 370 cases), the passrate were about 2101(288)/2643 with compiz enabled. (it's 2103(288)/2645 with compiz disabled). On ogles2 conformance side, there will be a lot of GPU hangs when enabled compiz.(compiz can't start without Jesse's patch) When disabled compiz, its passrate will return to 1194/1198 both with and without the patch in Kernel. 

Commit info:
Libdrm:         (master)2.4.26
Mesa:           (master)8875dd58719b978283e89acf04422a4eaf9b021d
Xserver:                (server-1.10-branch)xorg-server-1.10.2.901-2-g9fab8b475de99848866c07bde962a5f6ed01b987
Xf86_video_intel:               (master)2.15.0-125-g8fb98e22a63a4354b049ace7870abb6406541c28
Cairo:          (master)441f9c5037dd32464bd87e21108b702c0a3c508a
Libva:          (master)20574567f32a6ad9f46665a4ced5725df42355f1
Kernel:         (drm-intel-fixes)6a574b5b9b186e28abd3e571dfd1700c5220b510 + Jesse's patch 

> -----Original Message-----
> From: intel-gfx-bounces+jian.j.zhao=intel.com@lists.freedesktop.org
> [mailto:intel-gfx-bounces+jian.j.zhao=intel.com@lists.freedesktop.org] On
> Behalf Of Zhao, Jian J
> Sent: Monday, June 20, 2011 11:15 PM
> To: Jesse Barnes
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] IVB page flipping fixes (hopefully final)
> 
> Hi Jesse,
>  With your these two patches:
> http://lists.freedesktop.org/archives/intel-gfx/2011-June/011014.html It
> indeed fixed three bugs(#38362, #38392, #38393) on IvyBridge, but it also
> caused a regression(bug #38428) and another issue is with the patched
> kernel, the piglit cases' passrate dropped a lot, it changed from
> 2372(400)/3020 to 1682(397)/3020. The format is PASS(Not Supported)/Total.
> Though I find some crashed cases can't be reproduced when tested
> separately now. I will have an investigate on it. It is better if you could have
> some idea of the relation between the patch and piglit tests. Thanks.
> 
> Best regards
> zhaojian
> 
> > -----Original Message-----
> > From: intel-gfx-bounces+jian.j.zhao=intel.com@lists.freedesktop.org
> > [mailto:intel-gfx-bounces+jian.j.zhao=intel.com@lists.freedesktop.org] On
> > Behalf Of Jesse Barnes
> > Sent: Friday, June 17, 2011 12:19 AM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] IVB page flipping fixes (hopefully final)
> >
> > This set addresses comments from Dan and Chris, namely:
> >   - pin & fence the new fb on the correct ring for IVB
> >   - cleanup gen2/3 wait code by putting it in gen2/3 wait functions
> >   - remove dead code
> >   - fix a race in the split code with the interrupt handler and flip pending
> >
> > Thanks,
> > Jesse
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx