* [PATCH][RFC][1/2] x86 SMP: enables core-pair topology detection for AMD CPUs
@ 2011-06-23 22:52 Wei Huang
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From: Wei Huang @ 2011-06-23 22:52 UTC (permalink / raw)
To: 'xen-devel@lists.xensource.com', Keir Fraser,
george.dunlap, Jan Beulich
[-- Attachment #1: Type: text/plain, Size: 248 bytes --]
SMP: consolidate cpu_core_id and phys_proc_id into cpuinfo_x86 struct
This patch moves cpu_core_id and phys_proc_id into cpuinfo_x86
structure. This is similar to upstream Linux kernel's approach.
Signed-off-by: Wei Huang <wei.huang2@amd.com>
[-- Attachment #2: core_pair_1.txt --]
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# HG changeset patch
# User Wei Huang <wei.huang2@amd.com>
# Date 1308596799 18000
# Node ID fa1819d018e6e080ab273e96544dc042a5b8b00c
# Parent ebc1054b6563227db4604d273514941c72738511
SMP: consolidate cpu_core_id and phys_proc_id into cpuinfo_x86 struct
This patch moves cpu_core_id and phys_proc_id into cpuinfo_x86 structure. This is similar to upstream Linux kernel's approach.
Signed-off-by: Wei Huang <wei.huang2@amd.com>
diff -r ebc1054b6563 -r fa1819d018e6 xen/arch/x86/cpu/amd.c
--- a/xen/arch/x86/cpu/amd.c Mon Jun 20 14:02:52 2011 -0500
+++ b/xen/arch/x86/cpu/amd.c Mon Jun 20 14:06:39 2011 -0500
@@ -446,11 +446,11 @@
while ((1 << bits) < c->x86_max_cores)
bits++;
}
- cpu_core_id[cpu] = phys_proc_id[cpu] & ((1<<bits)-1);
- phys_proc_id[cpu] >>= bits;
+ c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
+ c->phys_proc_id >>= bits;
if (opt_cpu_info)
printk("CPU %d(%d) -> Core %d\n",
- cpu, c->x86_max_cores, cpu_core_id[cpu]);
+ cpu, c->x86_max_cores, c->cpu_core_id);
}
#endif
diff -r ebc1054b6563 -r fa1819d018e6 xen/arch/x86/cpu/common.c
--- a/xen/arch/x86/cpu/common.c Mon Jun 20 14:02:52 2011 -0500
+++ b/xen/arch/x86/cpu/common.c Mon Jun 20 14:06:39 2011 -0500
@@ -271,7 +271,7 @@
early_intel_workaround(c);
#ifdef CONFIG_X86_HT
- phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
+ c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
#endif
}
@@ -316,6 +316,8 @@
c->x86_max_cores = 1;
c->x86_num_siblings = 1;
c->x86_clflush_size = 0;
+ c->phys_proc_id = BAD_APICID;
+ c->cpu_core_id = BAD_APICID;
memset(&c->x86_capability, 0, sizeof c->x86_capability);
generic_identify(c);
@@ -453,7 +455,6 @@
unsigned int ht_mask_width, core_plus_mask_width;
unsigned int core_select_mask, core_level_siblings;
unsigned int initial_apicid;
- int cpu = smp_processor_id();
if ( c->cpuid_level < 0xb )
return;
@@ -488,9 +489,9 @@
core_select_mask = (~(-1 << core_plus_mask_width)) >> ht_mask_width;
- cpu_core_id[cpu] = phys_pkg_id(initial_apicid, ht_mask_width)
+ c->cpu_core_id = phys_pkg_id(initial_apicid, ht_mask_width)
& core_select_mask;
- phys_proc_id[cpu] = phys_pkg_id(initial_apicid, core_plus_mask_width);
+ c->phys_proc_id = phys_pkg_id(initial_apicid, core_plus_mask_width);
c->apicid = phys_pkg_id(initial_apicid, 0);
c->x86_max_cores = (core_level_siblings / c->x86_num_siblings);
@@ -498,10 +499,10 @@
if ( opt_cpu_info )
{
printk("CPU: Physical Processor ID: %d\n",
- phys_proc_id[cpu]);
+ c->phys_proc_id);
if ( c->x86_max_cores > 1 )
printk("CPU: Processor Core ID: %d\n",
- cpu_core_id[cpu]);
+ c->cpu_core_id);
}
}
@@ -510,7 +511,6 @@
{
u32 eax, ebx, ecx, edx;
int index_msb, core_bits;
- int cpu = smp_processor_id();
cpuid(1, &eax, &ebx, &ecx, &edx);
@@ -533,11 +533,11 @@
}
index_msb = get_count_order(c->x86_num_siblings);
- phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
+ c->phys_proc_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
if (opt_cpu_info)
printk("CPU: Physical Processor ID: %d\n",
- phys_proc_id[cpu]);
+ c->phys_proc_id);
c->x86_num_siblings = c->x86_num_siblings / c->x86_max_cores;
@@ -545,12 +545,12 @@
core_bits = get_count_order(c->x86_max_cores);
- cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
+ c->cpu_core_id = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
((1 << core_bits) - 1);
if (opt_cpu_info && c->x86_max_cores > 1)
printk("CPU: Processor Core ID: %d\n",
- cpu_core_id[cpu]);
+ c->cpu_core_id);
}
}
#endif
diff -r ebc1054b6563 -r fa1819d018e6 xen/arch/x86/cpu/mcheck/mce.c
--- a/xen/arch/x86/cpu/mcheck/mce.c Mon Jun 20 14:02:52 2011 -0500
+++ b/xen/arch/x86/cpu/mcheck/mce.c Mon Jun 20 14:06:39 2011 -0500
@@ -1046,9 +1046,9 @@
if (nthreads != NULL)
*nthreads = 1;
} else {
- *chipid = phys_proc_id[cpu];
+ *chipid = c->phys_proc_id;
if (c->x86_max_cores > 1)
- *coreid = cpu_core_id[cpu];
+ *coreid = c->cpu_core_id;
else
*coreid = 0;
*threadid = c->apicid & ((1 << (c->x86_num_siblings - 1)) - 1);
diff -r ebc1054b6563 -r fa1819d018e6 xen/arch/x86/smpboot.c
--- a/xen/arch/x86/smpboot.c Mon Jun 20 14:02:52 2011 -0500
+++ b/xen/arch/x86/smpboot.c Mon Jun 20 14:06:39 2011 -0500
@@ -49,12 +49,6 @@
#define setup_trampoline() (bootsym_phys(trampoline_realmode_entry))
-/* Package ID of each logical CPU */
-int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
-
-/* Core ID of each logical CPU */
-int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
-
/* representing HT siblings of each logical CPU */
DEFINE_PER_CPU_READ_MOSTLY(cpumask_t, cpu_sibling_map);
/* representing HT and core siblings of each logical CPU */
@@ -247,8 +241,8 @@
{
for_each_cpu_mask ( i, cpu_sibling_setup_map )
{
- if ( (phys_proc_id[cpu] == phys_proc_id[i]) &&
- (cpu_core_id[cpu] == cpu_core_id[i]) )
+ if ( (c[cpu].phys_proc_id == c[i].phys_proc_id) &&
+ (c[cpu].cpu_core_id == c[i].cpu_core_id) )
{
cpu_set(i, per_cpu(cpu_sibling_map, cpu));
cpu_set(cpu, per_cpu(cpu_sibling_map, i));
@@ -271,7 +265,7 @@
for_each_cpu_mask ( i, cpu_sibling_setup_map )
{
- if ( phys_proc_id[cpu] == phys_proc_id[i] )
+ if ( c[cpu].phys_proc_id == c[i].phys_proc_id )
{
cpu_set(i, per_cpu(cpu_core_map, cpu));
cpu_set(cpu, per_cpu(cpu_core_map, i));
@@ -832,8 +826,8 @@
cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
cpus_clear(per_cpu(cpu_sibling_map, cpu));
cpus_clear(per_cpu(cpu_core_map, cpu));
- phys_proc_id[cpu] = BAD_APICID;
- cpu_core_id[cpu] = BAD_APICID;
+ c[cpu].phys_proc_id = BAD_APICID;
+ c[cpu].cpu_core_id = BAD_APICID;
cpu_clear(cpu, cpu_sibling_setup_map);
}
diff -r ebc1054b6563 -r fa1819d018e6 xen/include/asm-x86/processor.h
--- a/xen/include/asm-x86/processor.h Mon Jun 20 14:02:52 2011 -0500
+++ b/xen/include/asm-x86/processor.h Mon Jun 20 14:06:39 2011 -0500
@@ -175,6 +175,8 @@
__u32 x86_max_cores; /* cpuid returned max cores value */
__u32 booted_cores; /* number of cores as seen by OS */
__u32 x86_num_siblings; /* cpuid logical cpus per chip value */
+ int phys_proc_id; /* package ID of each logical CPU */
+ int cpu_core_id; /* core ID of each logical CPU*/
__u32 apicid;
unsigned short x86_clflush_size;
} __cacheline_aligned;
@@ -194,8 +196,6 @@
#endif
extern u64 host_pat;
-extern int phys_proc_id[NR_CPUS];
-extern int cpu_core_id[NR_CPUS];
extern bool_t opt_cpu_info;
/* Maximum width of physical addresses supported by the hardware */
@@ -215,8 +215,8 @@
static always_inline void detect_ht(struct cpuinfo_x86 *c) {}
#endif
-#define cpu_to_core(_cpu) (cpu_core_id[_cpu])
-#define cpu_to_socket(_cpu) (phys_proc_id[_cpu])
+#define cpu_to_core(_cpu) (cpu_data[_cpu].cpu_core_id)
+#define cpu_to_socket(_cpu) (cpu_data[_cpu].phys_proc_id)
/*
* Generic CPUID function
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2011-06-23 22:52 [PATCH][RFC][1/2] x86 SMP: enables core-pair topology detection for AMD CPUs Wei Huang
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