From: "Cousson, Benoit" <b-cousson@ti.com>
To: "Shilimkar, Santosh" <santosh.shilimkar@ti.com>
Cc: "Taneja, Archit" <archit@ti.com>,
"linux-omap@vger.kernel.org" <linux-omap@vger.kernel.org>
Subject: Re: [PATCH] OMAP: ctrl: Fix CONTROL_DSIPHY register fields
Date: Wed, 27 Jul 2011 11:06:11 +0200 [thread overview]
Message-ID: <4E2FD503.7080505@ti.com> (raw)
In-Reply-To: <4E2FAE64.7020806@ti.com>
On 7/27/2011 8:21 AM, Shilimkar, Santosh wrote:
> + Benoit
Thanks Santosh,
Archit,
Could you please send your patch to all the authors of the file, including the maintainers?
Without Santosh, I would have missed that one, that seems to highlight a bug in the HW description DB. So it is quite critical to capture such issue ASAP with HW designers.
> On 7/27/2011 11:50 AM, Archit Taneja wrote:
>> Fix the shift and mask macros for DSIx_PPID fields in CONTROL_DSIPHY. The Latest
>> TRM mentions the correct fields in the register.
> You can mention the TRM version instead of 'latest'
> Latest is very much relative :)
>
>>
>> Signed-off-by: Archit Taneja<archit@ti.com>
> Change looks good to me.
> Autogen scripts needs to be checked as well.
>
>> ---
>> .../include/mach/ctrl_module_pad_core_44xx.h | 8 ++++----
>> 1 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
>> index c88420d..8321add 100644
>> --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
>> +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
>> @@ -941,10 +941,10 @@
>> #define OMAP4_DSI2_LANEENABLE_MASK (0x7<< 29)
>> #define OMAP4_DSI1_LANEENABLE_SHIFT 24
>> #define OMAP4_DSI1_LANEENABLE_MASK (0x1f<< 24)
>> -#define OMAP4_DSI1_PIPD_SHIFT 19
>> -#define OMAP4_DSI1_PIPD_MASK (0x1f<< 19)
>> -#define OMAP4_DSI2_PIPD_SHIFT 14
>> -#define OMAP4_DSI2_PIPD_MASK (0x1f<< 14)
>> +#define OMAP4_DSI1_PIPD_SHIFT 14
>> +#define OMAP4_DSI1_PIPD_MASK (0x1f<< 14)
>> +#define OMAP4_DSI2_PIPD_SHIFT 19
>> +#define OMAP4_DSI2_PIPD_MASK (0x1f<< 19)
Minor comment, but since this is sorted per shift value, the order should be:
+#define OMAP4_DSI2_PIPD_SHIFT 19
+#define OMAP4_DSI2_PIPD_MASK (0x1f << 19)
+#define OMAP4_DSI1_PIPD_SHIFT 14
+#define OMAP4_DSI1_PIPD_MASK (0x1f << 14)
Once you fix the changelog with Santosh comment, put the proper people in the TO list, and fix the order, you can add:
Acked-by: Benoit Cousson <b-cousson@ti.com>
Regards,
Benoit
prev parent reply other threads:[~2011-07-27 9:06 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-27 6:20 [PATCH] OMAP: ctrl: Fix CONTROL_DSIPHY register fields Archit Taneja
2011-07-27 6:21 ` Santosh Shilimkar
2011-07-27 9:06 ` Cousson, Benoit [this message]
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