[PATCH] MIPS: Netlogic: Minor fixes for XLR processors

[PATCH] MIPS: Netlogic: Minor fixes for XLR processors

[Jayachandran C]

* Avoid unneeded cache flushes, XLR dcache is fully coherent across
  CPUs.
* add r4k_wait as the cpu_wait
* Move load address - the current value wastes space.
---
 .../asm/mach-netlogic/cpu-feature-overrides.h      |    5 ++---
 arch/mips/kernel/cpu-probe.c                       |    1 +
 arch/mips/netlogic/Platform                        |    2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index 3b72827..3780743 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -25,13 +25,12 @@
 #define cpu_has_llsc		1
 #define cpu_has_vtag_icache	0
 #define cpu_has_dc_aliases	0
-#define cpu_has_ic_fills_f_dc	0
+#define cpu_has_ic_fills_f_dc	1
 #define cpu_has_dsp		0
 #define cpu_has_mipsmt		0
 #define cpu_has_userlocal	0
-#define cpu_icache_snoops_remote_store	0
+#define cpu_icache_snoops_remote_store	1
 
-#define cpu_has_nofpuex		0
 #define cpu_has_64bits		1
 
 #define cpu_has_mips32r1	1
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ebc0cd2..664bc13 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -190,6 +190,7 @@ void __init check_wait(void)
 	case CPU_CAVIUM_OCTEON_PLUS:
 	case CPU_CAVIUM_OCTEON2:
 	case CPU_JZRISC:
+	case CPU_XLR:
 		cpu_wait = r4k_wait;
 		break;
 
diff --git a/arch/mips/netlogic/Platform b/arch/mips/netlogic/Platform
index b648b48..502d912 100644
--- a/arch/mips/netlogic/Platform
+++ b/arch/mips/netlogic/Platform
@@ -13,4 +13,4 @@ cflags-$(CONFIG_NLM_XLR)	+= $(call cc-option,-march=xlr,-march=mips64)
 # NETLOGIC XLR/XLS SoC, Simulator and boards
 #
 core-$(CONFIG_NLM_XLR)	      += arch/mips/netlogic/xlr/
-load-$(CONFIG_NLM_XLR_BOARD)  += 0xffffffff84000000
+load-$(CONFIG_NLM_XLR_BOARD)  += 0xffffffff80100000
-- 
1.7.4.1

Re: [PATCH] MIPS: Netlogic: Minor fixes for XLR processors

[Sergei Shtylyov]

Hello.

On 30-07-2011 15:04, Jayachandran C wrote:

> * Avoid unneeded cache flushes, XLR dcache is fully coherent across
>    CPUs.
> * add r4k_wait as the cpu_wait
> * Move load address - the current value wastes space.

    This seems like a material for the whole 3 patches...

WBR, Sergei