From: robherring2@gmail.com (Rob Herring)
To: linux-arm-kernel@lists.infradead.org
Subject: Subject: L2x0 OF properties do not include interrupt #
Date: Wed, 10 Aug 2011 09:37:26 -0500 [thread overview]
Message-ID: <4E4297A6.6050101@gmail.com> (raw)
In-Reply-To: <20110810141048.GK10121@e102144-lin.cambridge.arm.com>
On 08/10/2011 09:10 AM, Will Deacon wrote:
> Hi Rob,
>
> On Wed, Aug 10, 2011 at 02:59:12PM +0100, Rob Herring wrote:
>> I think you should allow for either the single irq or individual irqs.
>> You can specify that the event counter interrupt must be first, then the
>> pmu driver could work either way ignoring the rest. The driver probably
>> needs to mark the handler as shared if there is only the combined
>> interrupt unless you expect all interrupts to be handled by 1 driver.
>
> I much prefer having seperate, individual IRQs with no requirement on
> ordering.
>
> Now, the L2 binding also doesn't fit too well for the L2CC on Cortex-A15,
> which is an inner cache like the one on Cortex-A8. Because of this, it
> doesn't have a base address but it *does* have an IRQ which is how external
> aborts are raised.
This is not a general L2 binding, but an L2x0/PL310 binding. A8/A15 L2
is a completely different binding and driver though. You would do
something like the current cpu pmu binding that is just interrupts.
Rob
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robherring2@gmail.com>
To: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <Mark.Rutland@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree-discuss@lists.ozlabs.org"
<devicetree-discuss@lists.ozlabs.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux@arm.linux.org.uk" <linux@arm.linux.org.uk>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"weizeng.he@csr.com" <weizeng.he@csr.com>,
"workgroup.linux@csr.com" <workgroup.linux@csr.com>,
"'Arnd Bergmann'" <arnd@arndb.de>,
"'Barry Song'" <21cnbao@gmail.com>,
"'Grant Likely'" <grant.likely@secretlab.ca>,
"'Olof Johansson'" <olof@lixom.net>
Subject: Re: Subject: L2x0 OF properties do not include interrupt #
Date: Wed, 10 Aug 2011 09:37:26 -0500 [thread overview]
Message-ID: <4E4297A6.6050101@gmail.com> (raw)
In-Reply-To: <20110810141048.GK10121@e102144-lin.cambridge.arm.com>
On 08/10/2011 09:10 AM, Will Deacon wrote:
> Hi Rob,
>
> On Wed, Aug 10, 2011 at 02:59:12PM +0100, Rob Herring wrote:
>> I think you should allow for either the single irq or individual irqs.
>> You can specify that the event counter interrupt must be first, then the
>> pmu driver could work either way ignoring the rest. The driver probably
>> needs to mark the handler as shared if there is only the combined
>> interrupt unless you expect all interrupts to be handled by 1 driver.
>
> I much prefer having seperate, individual IRQs with no requirement on
> ordering.
>
> Now, the L2 binding also doesn't fit too well for the L2CC on Cortex-A15,
> which is an inner cache like the one on Cortex-A8. Because of this, it
> doesn't have a base address but it *does* have an IRQ which is how external
> aborts are raised.
This is not a general L2 binding, but an L2x0/PL310 binding. A8/A15 L2
is a completely different binding and driver though. You would do
something like the current cpu pmu binding that is just interrupts.
Rob
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robherring2@gmail.com>
To: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <Mark.Rutland@arm.com>,
"linux@arm.linux.org.uk" <linux@arm.linux.org.uk>,
'Arnd Bergmann' <arnd@arndb.de>,
"devicetree-discuss@lists.ozlabs.org"
<devicetree-discuss@lists.ozlabs.org>,
'Barry Song' <21cnbao@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"workgroup.linux@csr.com" <workgroup.linux@csr.com>,
'Grant Likely' <grant.likely@secretlab.ca>,
"weizeng.he@csr.com" <weizeng.he@csr.com>,
'Olof Johansson' <olof@lixom.net>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: Subject: L2x0 OF properties do not include interrupt #
Date: Wed, 10 Aug 2011 09:37:26 -0500 [thread overview]
Message-ID: <4E4297A6.6050101@gmail.com> (raw)
In-Reply-To: <20110810141048.GK10121@e102144-lin.cambridge.arm.com>
On 08/10/2011 09:10 AM, Will Deacon wrote:
> Hi Rob,
>
> On Wed, Aug 10, 2011 at 02:59:12PM +0100, Rob Herring wrote:
>> I think you should allow for either the single irq or individual irqs.
>> You can specify that the event counter interrupt must be first, then the
>> pmu driver could work either way ignoring the rest. The driver probably
>> needs to mark the handler as shared if there is only the combined
>> interrupt unless you expect all interrupts to be handled by 1 driver.
>
> I much prefer having seperate, individual IRQs with no requirement on
> ordering.
>
> Now, the L2 binding also doesn't fit too well for the L2CC on Cortex-A15,
> which is an inner cache like the one on Cortex-A8. Because of this, it
> doesn't have a base address but it *does* have an IRQ which is how external
> aborts are raised.
This is not a general L2 binding, but an L2x0/PL310 binding. A8/A15 L2
is a completely different binding and driver though. You would do
something like the current cpu pmu binding that is just interrupts.
Rob
next prev parent reply other threads:[~2011-08-10 14:37 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-08-10 12:48 Subject: L2x0 OF properties do not include interrupt # Mark Rutland
2011-08-10 13:59 ` Rob Herring
2011-08-10 13:59 ` Rob Herring
2011-08-10 13:59 ` Rob Herring
2011-08-10 14:10 ` Will Deacon
2011-08-10 14:10 ` Will Deacon
2011-08-10 14:24 ` Arnd Bergmann
2011-08-10 14:24 ` Arnd Bergmann
2011-08-10 14:24 ` Arnd Bergmann
2011-08-10 14:28 ` Will Deacon
2011-08-10 14:28 ` Will Deacon
2011-08-10 14:28 ` Will Deacon
2011-08-11 13:05 ` Arnd Bergmann
2011-08-11 13:05 ` Arnd Bergmann
2011-08-11 13:05 ` Arnd Bergmann
2011-08-11 13:09 ` Will Deacon
2011-08-11 13:09 ` Will Deacon
2011-08-11 13:09 ` Will Deacon
2011-08-11 15:32 ` Rob Herring
2011-08-11 15:32 ` Rob Herring
2011-08-11 15:38 ` Will Deacon
2011-08-11 15:38 ` Will Deacon
2011-08-11 16:06 ` Rob Herring
2011-08-11 16:06 ` Rob Herring
2011-08-11 16:06 ` Rob Herring
2011-08-11 16:34 ` Will Deacon
2011-08-11 16:34 ` Will Deacon
2011-08-12 9:02 ` Russell King - ARM Linux
2011-08-12 9:02 ` Russell King - ARM Linux
2011-08-12 9:02 ` Russell King - ARM Linux
2011-08-10 14:37 ` Rob Herring [this message]
2011-08-10 14:37 ` Rob Herring
2011-08-10 14:37 ` Rob Herring
2011-08-10 14:39 ` Will Deacon
2011-08-10 14:39 ` Will Deacon
2011-08-10 14:39 ` Will Deacon
2011-08-10 14:09 ` Arnd Bergmann
2011-08-10 14:09 ` Arnd Bergmann
2011-08-10 14:09 ` Arnd Bergmann
2011-08-10 14:31 ` Rob Herring
2011-08-10 14:31 ` Rob Herring
2011-08-10 14:31 ` Rob Herring
2011-08-10 15:12 ` Will Deacon
2011-08-10 15:12 ` Will Deacon
2011-08-10 15:12 ` Will Deacon
-- strict thread matches above, loose matches on Subject: below --
2011-08-10 12:48 Mark Rutland
2011-08-10 12:48 Mark Rutland
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