* MIPS: Octeon: mailbox_interrupt is not registered as per cpu
@ 2011-09-05 10:23 SAURABH MALPANI
2011-09-06 18:38 ` David Daney
0 siblings, 1 reply; 6+ messages in thread
From: SAURABH MALPANI @ 2011-09-05 10:23 UTC (permalink / raw)
To: linux-mips
Hi,
<Re sending this because last time I am afraid I didn't hit the
correct mail filters.>
Query:
mailbox_interrupt is not registered with IRQF_PERCPU but it is
supposed to be percpu interrupt. Is that on purpose or a miss? I am
porting some code from x86 to octeon which requires special handling
for per cpu interrupts.
void octeon_prepare_cpus(unsigned int max_cpus)
{
cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
"mailbox0", mailbox_interrupt)) {
panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
}
if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED,
"mailbox1", mailbox_interrupt)) {
panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
}
}
--
Saurabh
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: MIPS: Octeon: mailbox_interrupt is not registered as per cpu
2011-09-05 10:23 MIPS: Octeon: mailbox_interrupt is not registered as per cpu SAURABH MALPANI
@ 2011-09-06 18:38 ` David Daney
2011-09-06 19:02 ` SAURABH MALPANI
0 siblings, 1 reply; 6+ messages in thread
From: David Daney @ 2011-09-06 18:38 UTC (permalink / raw)
To: SAURABH MALPANI; +Cc: linux-mips
On 09/05/2011 03:23 AM, SAURABH MALPANI wrote:
> Hi,
>
> <Re sending this because last time I am afraid I didn't hit the
> correct mail filters.>
>
> Query:
>
> mailbox_interrupt is not registered with IRQF_PERCPU but it is
> supposed to be percpu interrupt. Is that on purpose or a miss?
On Octeon the per-cpuness of a particular irq is a property of the irq
itself rather than being controlled by IRQF_PERCPU. So other than being
perhaps stylistically in poor taste, no harm is done by omitting
IRQF_PERCPU here.
> I am
> porting some code from x86 to octeon which requires special handling
> for per cpu interrupts.
>
> void octeon_prepare_cpus(unsigned int max_cpus)
> {
> cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
> if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
> "mailbox0", mailbox_interrupt)) {
> panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
> }
> if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED,
> "mailbox1", mailbox_interrupt)) {
> panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
> }
> }
>
> --
> Saurabh
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: MIPS: Octeon: mailbox_interrupt is not registered as per cpu
2011-09-06 18:38 ` David Daney
@ 2011-09-06 19:02 ` SAURABH MALPANI
2011-09-06 19:17 ` David Daney
0 siblings, 1 reply; 6+ messages in thread
From: SAURABH MALPANI @ 2011-09-06 19:02 UTC (permalink / raw)
To: David Daney; +Cc: linux-mips
Hi David,
Thanks a bunch for clarifying this. Just to complete, I have some code
which calls CHECK_IRQ_PER_CPU(desc->status) after every time a
descriptor is created for an irq. And based on it we create either per
cpu data structures or single data structure for that particular irq.
After your clarification, I can safely create exception for
OCTEON_IRQ_MBOX0 and OCTEON_IRQ_MBOX1 as you mention that missing the
flag is just cosmetic.
Thanks again
Saurabh
On Wed, Sep 7, 2011 at 12:08 AM, David Daney <david.daney@cavium.com> wrote:
> On 09/05/2011 03:23 AM, SAURABH MALPANI wrote:
>>
>> Hi,
>>
>> <Re sending this because last time I am afraid I didn't hit the
>> correct mail filters.>
>>
>> Query:
>>
>> mailbox_interrupt is not registered with IRQF_PERCPU but it is
>> supposed to be percpu interrupt. Is that on purpose or a miss?
>
> On Octeon the per-cpuness of a particular irq is a property of the irq
> itself rather than being controlled by IRQF_PERCPU. So other than being
> perhaps stylistically in poor taste, no harm is done by omitting IRQF_PERCPU
> here.
>
>> I am
>> porting some code from x86 to octeon which requires special handling
>> for per cpu interrupts.
>>
>> void octeon_prepare_cpus(unsigned int max_cpus)
>> {
>> cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()),
>> 0xffffffff);
>> if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
>> IRQF_DISABLED,
>> "mailbox0", mailbox_interrupt)) {
>> panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
>> }
>> if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt,
>> IRQF_DISABLED,
>> "mailbox1", mailbox_interrupt)) {
>> panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
>> }
>> }
>>
>> --
>> Saurabh
>>
>>
>
>
--
Saurabh
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: MIPS: Octeon: mailbox_interrupt is not registered as per cpu
2011-09-06 19:02 ` SAURABH MALPANI
@ 2011-09-06 19:17 ` David Daney
2011-09-06 19:21 ` SAURABH MALPANI
0 siblings, 1 reply; 6+ messages in thread
From: David Daney @ 2011-09-06 19:17 UTC (permalink / raw)
To: SAURABH MALPANI; +Cc: linux-mips
On 09/06/2011 12:02 PM, SAURABH MALPANI wrote:
> Hi David,
>
> Thanks a bunch for clarifying this. Just to complete, I have some code
> which calls CHECK_IRQ_PER_CPU(desc->status) after every time a
> descriptor is created for an irq. And based on it we create either per
> cpu data structures or single data structure for that particular irq.
>
> After your clarification, I can safely create exception for
> OCTEON_IRQ_MBOX0 and OCTEON_IRQ_MBOX1 as you mention that missing the
> flag is just cosmetic.
>
Well the performance counter and timer interrupts may suffer in a
similar manner.
David Daney
> Thanks again
> Saurabh
>
>
> On Wed, Sep 7, 2011 at 12:08 AM, David Daney<david.daney@cavium.com> wrote:
>> On 09/05/2011 03:23 AM, SAURABH MALPANI wrote:
>>>
>>> Hi,
>>>
>>> <Re sending this because last time I am afraid I didn't hit the
>>> correct mail filters.>
>>>
>>> Query:
>>>
>>> mailbox_interrupt is not registered with IRQF_PERCPU but it is
>>> supposed to be percpu interrupt. Is that on purpose or a miss?
>>
>> On Octeon the per-cpuness of a particular irq is a property of the irq
>> itself rather than being controlled by IRQF_PERCPU. So other than being
>> perhaps stylistically in poor taste, no harm is done by omitting IRQF_PERCPU
>> here.
>>
>>> I am
>>> porting some code from x86 to octeon which requires special handling
>>> for per cpu interrupts.
>>>
>>> void octeon_prepare_cpus(unsigned int max_cpus)
>>> {
>>> cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()),
>>> 0xffffffff);
>>> if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
>>> IRQF_DISABLED,
>>> "mailbox0", mailbox_interrupt)) {
>>> panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
>>> }
>>> if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt,
>>> IRQF_DISABLED,
>>> "mailbox1", mailbox_interrupt)) {
>>> panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
>>> }
>>> }
>>>
>>> --
>>> Saurabh
>>>
>>>
>>
>>
>
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: MIPS: Octeon: mailbox_interrupt is not registered as per cpu
2011-09-06 19:17 ` David Daney
@ 2011-09-06 19:21 ` SAURABH MALPANI
0 siblings, 0 replies; 6+ messages in thread
From: SAURABH MALPANI @ 2011-09-06 19:21 UTC (permalink / raw)
To: David Daney; +Cc: linux-mips
On Wed, Sep 7, 2011 at 12:47 AM, David Daney <david.daney@cavium.com> wrote:
> On 09/06/2011 12:02 PM, SAURABH MALPANI wrote:
>>
>> Hi David,
>>
>> Thanks a bunch for clarifying this. Just to complete, I have some code
>> which calls CHECK_IRQ_PER_CPU(desc->status) after every time a
>> descriptor is created for an irq. And based on it we create either per
>> cpu data structures or single data structure for that particular irq.
>>
>> After your clarification, I can safely create exception for
>> OCTEON_IRQ_MBOX0 and OCTEON_IRQ_MBOX1 as you mention that missing the
>> flag is just cosmetic.
>>
>
> Well the performance counter and timer interrupts may suffer in a similar
> manner.
>
> David Daney
>
Since the timer interrupt is registered via the clock device
infrastructure, I found that hrtimer_interrupt irq descriptor was
indeed succeeding the CHECK_IRQ_PER_CPU test. So far in our testing we
only hit an exception for mailbox interrupt.
^ permalink raw reply [flat|nested] 6+ messages in thread
* MIPS:Octeon: mailbox_interrupt is not registered as per cpu
@ 2011-09-02 7:59 SAURABH MALPANI
0 siblings, 0 replies; 6+ messages in thread
From: SAURABH MALPANI @ 2011-09-02 7:59 UTC (permalink / raw)
To: linux-mips
[-- Attachment #1: Type: text/plain, Size: 786 bytes --]
mailbox_interrupt is not registered with IRQF_PERCPU but it is supposed to
be percpu interrupt. Is that on purpose or a miss? I am porting some code
from x86 to octeon which requires special handling for per cpu interrupts.
void octeon_prepare_cpus(unsigned int max_cpus)
{
cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
"mailbox0", mailbox_interrupt)) {
panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
}
if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_DISABLED,
"mailbox1", mailbox_interrupt)) {
panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
}
}
--
Saurabh
[-- Attachment #2: Type: text/html, Size: 1079 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2011-09-06 19:22 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-09-05 10:23 MIPS: Octeon: mailbox_interrupt is not registered as per cpu SAURABH MALPANI
2011-09-06 18:38 ` David Daney
2011-09-06 19:02 ` SAURABH MALPANI
2011-09-06 19:17 ` David Daney
2011-09-06 19:21 ` SAURABH MALPANI
-- strict thread matches above, loose matches on Subject: below --
2011-09-02 7:59 MIPS:Octeon: " SAURABH MALPANI
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.