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* [U-Boot] [PATCH v2] Add support for IDS8313 boards
@ 2011-09-20  8:48 Sergej.Stepanov at ids.de
  2011-09-20 10:46 ` Heiko Schocher
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: Sergej.Stepanov at ids.de @ 2011-09-20  8:48 UTC (permalink / raw)
  To: u-boot

This patch adds support for IDS8313 boards based on MPC8313
It contains the following components:
- both of TSEC's, NOR- and NAND flash, I2C, SPI

Signed-off-by: Sergej Stepanov <ste@ids.de>
Signed-off-by: Rolf Riehle <rl@ids.de>
--
 board/ids/ids8313/Makefile  |   52 ++++
 board/ids/ids8313/ids8313.c |  170 +++++++++++++
 boards.cfg                  |    1 +
 include/configs/IDS8313.h   |  575 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 798 insertions(+), 0 deletions(-)

diff --git a/board/ids/ids8313/Makefile b/board/ids/ids8313/Makefile
new file mode 100644
index 0000000..4bd325b
--- /dev/null
+++ b/board/ids/ids8313/Makefile
@@ -0,0 +1,52 @@
+#
+# Copyright (c) 2011 IDS GmbH, Germany
+#
+# Sergej Stepanov <ste@ids.de>
+# Based on board/freescale/mpc8313erdb/Makefile
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := $(BOARD).o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c
new file mode 100644
index 0000000..0dc4919
--- /dev/null
+++ b/board/ids/ids8313/ids8313.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2011 IDS GmbH, Germany
+ * ids8313.c - ids8313 board support.
+ *
+ * Sergej Stepanov <ste@ids.de>
+ * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <spi.h>
+#include <libfdt.h>
+
+int checkboard(void)
+{
+       puts("Board: CX73X\n");
+       return 0;
+}
+
+/*************************************************************************
+ *  fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+int fixed_sdram(void)
+{
+       immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+       u32 msize = CONFIG_SYS_DDR_SIZE << 20;
+
+#if (CONFIG_SYS_DDR_SIZE != 128)
+#warning Currently any ddr size other than 256 is not supported
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+       u32 msize_log2 = __ilog2(msize);
+
+       out_be32(&im->sysconf.ddrlaw[0].bar,
+                (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+       out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+       out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+       sync();
+
+       /*
+        * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+        * or the DDR2 controller may fail to initialize correctly.
+        */
+       udelay(50000);
+
+       out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+       out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+
+       /* currently we use only one CS, so disable the other banks */
+       out_be32(&im->ddr.cs_config[1], 0);
+       out_be32(&im->ddr.cs_config[2], 0);
+       out_be32(&im->ddr.cs_config[3], 0);
+
+       out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+       out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+       out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+       out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+       out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
+       out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
+
+       out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+       out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
+
+       out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+       out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+       sync();
+       udelay(300);
+
+       /* enable DDR controller */
+       setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+       /* now check the real size */
+       disable_addr_trans();
+       msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
+       enable_addr_trans();
+#endif
+       return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+       immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+       fsl_lbc_t *lbc = &im->im_lbc;
+       u32 msize = 0;
+
+       if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+               return -1;
+
+       msize = fixed_sdram();
+
+       out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+       out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+       sync();
+
+       return msize;
+}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+       ft_cpu_setup(blob, bd);
+}
+#endif
+
+#define IDSCPLD_SPI_CS_MASK            0x00000001
+#define IDSCPLD_SPI_BUS_DEFAULT        2
+#define IDSCPLD_SPI_CS_BASE            0xE300000f
+
+#if defined(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+       gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+       u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+       *spi_base = 0;
+       iopd->dir |= IDSCPLD_SPI_CS_MASK;
+       return 0;
+}
+#endif
+
+#ifdef CONFIG_MPC8XXX_SPI
+/*
+ * The following are used to control the SPI chip selects
+ */
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+       return bus == 0 && ((cs >= 0) && (cs <= 2));
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+       gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+       u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+       *spi_base = (u8)1 << slave->cs;
+       iopd->dat &= ~IDSCPLD_SPI_CS_MASK;
+       sync();
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+       gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
+       u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
+
+       *spi_base = (u8)1 << slave->cs;
+       iopd->dat |=  IDSCPLD_SPI_CS_MASK;
+       sync();
+}
+#endif /* CONFIG_HARD_SPI */
diff --git a/boards.cfg b/boards.cfg
index 8a5bfc1..acec06b 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -536,6 +536,7 @@ suvd3                        powerpc     mpc83xx     km83xx              keymile
 TQM834x                      powerpc     mpc83xx     tqm834x             tqc
 tuda1                        powerpc     mpc83xx     km83xx              keymile
 tuxa1                        powerpc     mpc83xx     km83xx              keymile
+IDS8313                      powerpc     mpc83xx     ids8313             ids            -           IDS8313:SYS_TEXT_BASE=0xFFF00000
 sbc8540                      powerpc     mpc85xx     sbc8560             -              -           SBC8540
 sbc8540_33                   powerpc     mpc85xx     sbc8560             -              -           SBC8540
 sbc8540_66                   powerpc     mpc85xx     sbc8560             -              -           SBC8540
diff --git a/include/configs/IDS8313.h b/include/configs/IDS8313.h
new file mode 100644
index 0000000..284dc21
--- /dev/null
+++ b/include/configs/IDS8313.h
@@ -0,0 +1,575 @@
+
+/*
+ * Copyright (c) 2011 IDS GmbH, Germany
+ * Sergej Stepanov <ste@ids.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300                    1
+#define CONFIG_MPC83xx                 1
+#define CONFIG_MPC831x                 1
+#define CONFIG_MPC8313                 1
+#define CONFIG_IDS8313                 1
+
+#define CONFIG_FSL_ELBC                1
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_BOOTDELAY               5       /* autoboot after 5 seconds */
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT \
+       "\nEnter password - autoboot in %d seconds...\n", CONFIG_BOOTDELAY
+#define CONFIG_AUTOBOOT_DELAY_STR      "ids"
+#define CONFIG_BOOT_RETRY_TIME         900
+#define CONFIG_BOOT_RETRY_MIN          30
+
+#define CONFIG_83XX_CLKIN              66000000        /* in Hz */
+#define CONFIG_SYS_CLK_FREQ            CONFIG_83XX_CLKIN
+
+#define CONFIG_SYS_IMMR                0xF0000000
+
+#define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
+#define CONFIG_SYS_ACR_RPTCNT          3       /* Arbiter repeat count (0-7) */
+
+#define CONFIG_SYS_RCWH_PCIHOST        0x80000000      /* PCIHOST  */
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.000MHz, then
+ * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz?
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+       0x20000000 /* reserved, must be set */ |\
+       HRCWL_DDR_TO_SCB_CLK_2X1 |\
+       HRCWL_CSB_TO_CLKIN_2X1 |\
+       HRCWL_CORE_TO_CSB_2X1)
+
+#define CONFIG_SYS_HRCW_HIGH   (HRCWH_PCI_HOST |\
+                                HRCWH_CORE_ENABLE |\
+                                HRCWH_FROM_0XFFF00100 |\
+                                HRCWH_BOOTSEQ_DISABLE |\
+                                HRCWH_SW_WATCHDOG_DISABLE |\
+                                HRCWH_ROM_LOC_LOCAL_8BIT |\
+                                HRCWH_RL_EXT_LEGACY |\
+                                HRCWH_TSEC1M_IN_MII |\
+                                HRCWH_TSEC2M_IN_MII |\
+                                HRCWH_BIG_ENDIAN)
+
+#define CONFIG_SYS_SICRH       0x00000000
+#define CONFIG_SYS_SICRL       (SICRL_LBC | SICRL_SPI_D)
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SYS_HID0_INIT   0x000000000
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK |\
+                                HID0_ENABLE_INSTRUCTION_CACHE |\
+                                HID0_DISABLE_DYNAMIC_POWER_MANAGMENT)
+
+#define CONFIG_SYS_HID2        (HID2_HBE | 0x00020000)
+
+/*---------------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DCACHE )
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK       1
+#define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000
+#define CONFIG_SYS_INIT_RAM_SIZE       0x1000  /* End of used area in DPRAM */
+#define CONFIG_SYS_GBL_DATA_SIZE       0x100
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE \
+                                        - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CONFIG_SYS_LCRR_EADC   LCRR_EADC_1
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR    (0x00040000 |\
+                                (0xFF << LBCR_BMT_SHIFT) |\
+                                0xF)
+
+#define CONFIG_SYS_LBC_MRTPR   0x20000000
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD                  0x01
+#define BOOTFLAG_WARM                  0x02
+
+/* -------------------------------------------------------
+ * DDR Setup
+ * ------------------------------------------------------- */
+#define CONFIG_SYS_DDR_BASE            0x00000000
+#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+
+/*
+ * Manually set up DDR parameters,
+ * as this board has not the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE            128             /* MB */
+#define CONFIG_SYS_DDR_CONFIG          (CSCONFIG_EN |\
+                                        0x00010000 |\
+                                        CSCONFIG_ROW_BIT_13 |\
+                                        CSCONFIG_COL_BIT_10)
+
+#define CONFIG_SYS_DDR_TIMING_3        0x00000000
+#define CONFIG_SYS_DDR_TIMING_0        ((3<<TIMING_CFG0_RWT_SHIFT) |\
+                                        (3<<TIMING_CFG0_WRT_SHIFT) |\
+                                        (3<<TIMING_CFG0_RRT_SHIFT) |\
+                                        (3<<TIMING_CFG0_WWT_SHIFT) |\
+                                        (6<<TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\
+                                        (6<<TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\
+                                        (15<<TIMING_CFG0_ODT_PD_EXIT_SHIFT) |\
+                                        (4<<TIMING_CFG0_MRS_CYC_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_1        ((3<<TIMING_CFG1_PRETOACT_SHIFT) |\
+                                        (8<<TIMING_CFG1_ACTTOPRE_SHIFT) |\
+                                        (3<<TIMING_CFG1_ACTTORW_SHIFT) |\
+                                        (7<<TIMING_CFG1_CASLAT_SHIFT) |\
+                                        (15<<TIMING_CFG1_REFREC_SHIFT) |\
+                                        (3<<TIMING_CFG1_WRREC_SHIFT) |\
+                                        (3<<TIMING_CFG1_ACTTOACT_SHIFT) |\
+                                        (3<<TIMING_CFG1_WRTORD_SHIFT))
+#define CONFIG_SYS_DDR_TIMING_2        ((1<<TIMING_CFG2_ADD_LAT_SHIFT) |\
+                                        (5<<TIMING_CFG2_CPO_SHIFT) |   \
+                                        (4<<TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\
+                                        (4<<TIMING_CFG2_RD_TO_PRE_SHIFT) |\
+                                        (0<<TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\
+                                        (3<<TIMING_CFG2_CKE_PLS_SHIFT) |\
+                                        (6<<TIMING_CFG2_FOUR_ACT_SHIFT))
+
+#define CONFIG_SYS_DDR_INTERVAL        ((800 << SDRAM_INTERVAL_REFINT_SHIFT) |\
+                                        (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+
+#define CONFIG_SYS_SDRAM_CFG           (SDRAM_CFG_SREN |\
+                                        SDRAM_CFG_32_BE |\
+                                        SDRAM_CFG_SDRAM_TYPE_DDR2)
+
+#define CONFIG_SYS_SDRAM_CFG2          0x00401000
+#define CONFIG_SYS_DDR_MODE            ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\
+                                        (0x0242 << SDRAM_MODE_SD_SHIFT))
+#define CONFIG_SYS_DDR_MODE_2          0x00000000
+#define CONFIG_SYS_DDR_CLK_CNTL        DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075
+#define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN |\
+                                        DDRCDR_PZ_NOMZ |\
+                                        DDRCDR_NZ_NOMZ |\
+                                        DDRCDR_ODT |\
+                                        DDRCDR_M_ODR |\
+                                        DDRCDR_Q_DRN)
+
+/* --------------------------------------------------------------------------
+ * on-board devices
+ * -------------------------------------------------------------------------- */
+
+/*
+ * NOR FLASH setup
+ */
+#define CONFIG_SYS_FLASH_CFI           /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER        /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_8BIT
+#define CONFIG_FLASH_SHOW_PROGRESS     50
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE      1
+
+#define CONFIG_SYS_FLASH_BASE          0xFF800000
+#define CONFIG_SYS_FLASH_SIZE          8
+#define CONFIG_SYS_FLASH_PROTECTION    1
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM     0x80000016
+
+#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE  |\
+                               BR_PS_8         |\
+                               BR_MS_GPCM              |\
+                               BR_V)
+
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
+                               OR_GPCM_SCY_10 |\
+                               OR_GPCM_EHTR |\
+                               OR_GPCM_TRLX |\
+                               OR_GPCM_CSNT |\
+                               OR_GPCM_EAD)
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_MAX_FLASH_SECT      128
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500
+
+/* -------------------------------------------------------
+ * NAND FLASH setup
+ * ------------------------------------------------------- */
+#define CONFIG_SYS_NAND_BASE           0xE1000000
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_MAX_CHIPS 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_PAGE_SIZE      (2048)
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 << 10)
+#define NAND_CACHE_PAGES               64
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000000E
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+
+#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_NAND_BASE) |\
+                                (2<<BR_DECC_SHIFT) |\
+                                BR_PS_8 |\
+                                BR_MS_FCM |\
+                                BR_V)
+
+#define CONFIG_SYS_OR1_PRELIM  (0xFFFF8000 |\
+                                OR_FCM_PGS |\
+                                OR_FCM_CSCT |\
+                                OR_FCM_CST |\
+                                OR_FCM_CHT |\
+                                OR_FCM_SCY_4 |\
+                                OR_FCM_TRLX |\
+                                OR_FCM_EHTR |\
+                                OR_FCM_RST)
+
+/* -------------------------------------------------------
+ * MRAM setup
+ * ------------------------------------------------------- */
+#define CONFIG_SYS_MRAM_BASE           0xE2000000
+#define CONFIG_SYS_MRAM_SIZE           0x20000 /* 128 Kb */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM    CONFIG_SYS_MRAM_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM     0x80000010      /* 128 Kb  */
+
+#define CONFIG_SYS_OR_TIMING_MRAM
+
+#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_MRAM_BASE |\
+                                        BR_PS_8 |\
+                                        BR_MS_GPCM |\
+                                        BR_V)
+
+#define CONFIG_SYS_OR2_PRELIM          0xFFFE0C74
+
+/* -------------------------------------------------------
+ * CPLD setup
+ * ------------------------------------------------------- */
+#define CONFIG_SYS_CPLD_BASE           0xE3000000
+#define CONFIG_SYS_CPLD_SIZE           0x8000
+#define CONFIG_SYS_LBLAWBAR3_PRELIM    CONFIG_SYS_CPLD_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM     0x8000000E
+
+#define CONFIG_SYS_OR_TIMING_MRAM
+
+#define CONFIG_SYS_BR3_PRELIM          (CONFIG_SYS_CPLD_BASE |\
+                                        BR_PS_8 |\
+                                        BR_MS_GPCM |\
+                                        BR_V)
+
+#define CONFIG_SYS_OR3_PRELIM          0xFFFF8814
+
+/* -------------------------------------------------------
+ * I2C setup
+ * ------------------------------------------------------- */
+#define CONFIG_HARD_I2C
+#define CONFIG_FSL_I2C
+#define CONFIG_SYS_I2C_SPEED           400000
+#define CONFIG_SYS_I2C_OFFSET          0x3100
+#define CONFIG_SYS_I2C_SLAVE           0x7F
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR        0x51
+
+/* -------------------------------------------------------
+ * SPI setup
+ * ------------------------------------------------------- */
+#define CONFIG_HARD_SPI
+#define CONFIG_MPC8XXX_SPI
+#define CONFIG_CMD_SPI
+#undef CONFIG_SOFT_SPI
+
+#define CONFIG_SYS_GPIO1_PRELIM
+#define CONFIG_SYS_GPIO1_DIR           0x00000001
+#define CONFIG_SYS_GPIO1_DAT           0x00000001
+
+/* -------------------------------------------------------
+ * Ethernet setup
+ * ------------------------------------------------------- */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC2
+#define CONFIG_TSEC_ENET
+#define CONFIG_NET_MULTI
+
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME      "TSEC0"
+#define CONFIG_SYS_TSEC1_OFFSET        0x24000
+#define TSEC1_PHY_ADDR         0x1
+#define TSEC1_FLAGS            TSEC_GIGABIT
+#define TSEC1_PHYIDX           0
+#endif
+
+#ifdef CONFIG_TSEC2
+#define CONFIG_HAS_ETH1
+#define CONFIG_TSEC2_NAME              "TSEC1"
+#define CONFIG_SYS_TSEC2_OFFSET        0x25000
+#define TSEC2_PHY_ADDR                 0x3
+#define TSEC2_FLAGS                    TSEC_GIGABIT
+#define TSEC2_PHYIDX                   0
+#endif
+#define CONFIG_ETHPRIME                "TSEC1"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+
+#define CONFIG_SYS_BAUDRATE_TABLE      \
+       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
+#define CONFIG_SYS_NS16550_CLK         (CONFIG_83XX_CLKIN*2)
+
+#define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_SCCR_USBDRCM        3
+
+/* -----------------------------------------------------------
+ * BAT's
+ */
+#define CONFIG_HIGH_BATS       1
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L              (CONFIG_SYS_SDRAM_BASE |\
+                                        BATL_PP_10)
+#define CONFIG_SYS_IBAT0U              (CONFIG_SYS_SDRAM_BASE |\
+                                        BATU_BL_128M |\
+                                        BATU_VS |\
+                                        BATU_VP)
+#define CONFIG_SYS_DBAT0L              CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U              CONFIG_SYS_IBAT0U
+
+/* Initial RAM @ 0xFD000000 */
+#define CONFIG_SYS_IBAT1L              (CONFIG_SYS_INIT_RAM_ADDR |\
+                                        BATL_PP_10 |\
+                                        BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U              (CONFIG_SYS_INIT_RAM_ADDR |\
+                                        BATU_BL_256K |\
+                                        BATU_VS |\
+                                        BATU_VP)
+#define CONFIG_SYS_DBAT1L              CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U              CONFIG_SYS_IBAT1U
+
+/* FLASH @ 0xFF800000 */
+#define CONFIG_SYS_IBAT2L              (CONFIG_SYS_FLASH_BASE |\
+                                        BATL_PP_10 |\
+                                        BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U              (CONFIG_SYS_FLASH_BASE |\
+                                        BATU_BL_8M |\
+                                        BATU_VS |\
+                                        BATU_VP)
+#define CONFIG_SYS_DBAT2L              (CONFIG_SYS_FLASH_BASE |\
+                                        BATL_PP_10 |\
+                                        BATL_CACHEINHIBIT |\
+                                        BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U              CONFIG_SYS_IBAT2U
+
+#define CONFIG_SYS_IBAT3L              (0)
+#define CONFIG_SYS_IBAT3U              (0)
+#define CONFIG_SYS_DBAT3L              CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U              CONFIG_SYS_IBAT3U
+
+#define CONFIG_SYS_IBAT4L              (0)
+#define CONFIG_SYS_IBAT4U              (0)
+#define CONFIG_SYS_DBAT4L              CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U              CONFIG_SYS_IBAT4U
+
+/* IMMRBAR @ 0xF0000000 */
+#define CONFIG_SYS_IBAT5L              (CONFIG_SYS_IMMR |\
+                                        BATL_PP_10 |\
+                                        BATL_CACHEINHIBIT |\
+                                        BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U              (CONFIG_SYS_IMMR |\
+                                        BATU_BL_128M |\
+                                        BATU_VS |\
+                                        BATU_VP)
+#define CONFIG_SYS_DBAT5L              CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U              CONFIG_SYS_IBAT5U
+
+/* NAND-Flash @ 0xE1000000, MRAM @ 0xE2000000, CPLD @ 0xE3000000 */
+#define CONFIG_SYS_IBAT6L              (0xE0000000 |\
+                                        BATL_PP_10 |\
+                                        BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U              (0xE0000000 |\
+                                        BATU_BL_256M |\
+                                        BATU_VS |\
+                                        BATU_VP)
+#define CONFIG_SYS_DBAT6L              CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U              CONFIG_SYS_IBAT6U
+
+#define CONFIG_SYS_IBAT7L              (0)
+#define CONFIG_SYS_IBAT7U              (0)
+#define CONFIG_SYS_DBAT7L              CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U              CONFIG_SYS_IBAT7U
+
+/* -------------------------------------------------------
+ * U-Boot environment setup
+ * ------------------------------------------------------- */
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT               1
+#define CONFIG_OF_BOARD_SETUP          1
+#define CONFIG_OF_STDOUT_VIA_ALIAS     1
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN         (384*1024)
+#define CONFIG_SYS_MALLOC_LEN          (512*1024)
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH         1
+#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE \
+                                        + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE                0x20000
+
+#undef CONFIG_ENV_OVERWRITE
+
+#define CONFIG_NETDEV                  eth1
+#define CONFIG_HOSTNAME                ids8313
+#define CONFIG_ROOTPATH                "/opt/eldk-4.2/ppc_6xx"
+#define CONFIG_BOOTFILE                "ids8313/uImage"
+#define CONFIG_UBOOTPATH               "ids8313/u-boot.bin"
+#define CONFIG_FDTFILE                 "ids8313/ids8313.dtb"
+#define CONFIG_LOADADDR                0x400000
+#define CONFIG_BOOTDELAY               5
+#define CONFIG_BAUDRATE                115200
+
+/* watchdog disabled */
+#undef CONFIG_WATCHDOG
+#define CONFIG_SYS_HZ                  1000
+
+/* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ           (256 << 20)
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT              "=> "
+#define CONFIG_SYS_CBSIZE              1024
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE \
+                                        + sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START       0x00001000
+#define CONFIG_SYS_MEMTEST_END         0x00C00000
+
+#define CONFIG_SYS_LOAD_ADDR           0x100000
+#define CONFIG_MII
+#define CONFIG_LOADS_ECHO              1
+#define CONFIG_TIMESTAMP
+#define CONFIG_PREBOOT                 "echo;" \
+                                       "echo Type \\\"run nfsboot\\\" " \
+                                       "to mount root filesystem over NFS;echo"
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND             "run boot_cramfs"
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV               "0"
+#define CONFIG_SYS_JFFS2_OFF           "0"
+#define CONFIG_MTD_NAND_ECC_JFFS2
+
+/* mtdparts command line support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define MTDIDS_DEFAULT         "nor0=cu73x-0,nand0=cu73x-nand"
+#define MTDPARTS_DEFAULT       "mtdparts=cu73x-0:2M(kernel),5m(cramfs)," \
+                                       "384k(u-boot),128k(env);" \
+                               "cu78d-nand:96m(jffs2),32m(jffs2)"
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+#define XMK_STR(x)     #x
+#define MK_STR(x)      XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "netdev=" MK_STR(CONFIG_NETDEV) "\0"                            \
+       "ethprime=TSEC1\0"                                              \
+       "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
+       "tftpflash=tftpboot ${loadaddr} ${uboot}; "                     \
+               "protect off " MK_STR(TEXT_BASE) " +${filesize}; "      \
+               "erase " MK_STR(TEXT_BASE) " +${filesize}; "            \
+               "cp.b ${loadaddr} " MK_STR(TEXT_BASE) " ${filesize}; "  \
+               "protect on " MK_STR(TEXT_BASE) " +${filesize}; "       \
+               "cmp.b ${loadaddr} " MK_STR(TEXT_BASE) " ${filesize}\0" \
+       "console=ttyS0\0"                                       \
+       "fdtaddr=0x780000\0"                                            \
+       "kernel_addr=ff800000\0"                                        \
+       "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"                          \
+       "setbootargs=setenv bootargs "                                  \
+               "root=${rootdev} rw console=${console},"                \
+                       "${baudrate} ${othbootargs}\0"                  \
+       "setipargs=setenv bootargs root=${rootdev} rw "         \
+                       "nfsroot=${serverip}:${rootpath} "              \
+                       "ip=${ipaddr}:${serverip}:${gatewayip}:"        \
+                       "${netmask}:${hostname}:${netdev}:off " \
+                       "console=${console},${baudrate} ${othbootargs}\0"
+
+#define CONFIG_NFSBOOTCOMMAND                                          \
+       "setenv rootdev /dev/nfs;"                                      \
+       "run setipargs;"                                                \
+       "tftp ${loadaddr} ${bootfile};"                         \
+       "tftp ${fdtaddr} ${fdtfile};"                                   \
+       "fdt addr ${fdtaddr};"                                          \
+       "bootm ${loadaddr} - ${fdtaddr}"
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif /* __CONFIG_H */

^ permalink raw reply related	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2011-11-03 22:09 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-09-20  8:48 [U-Boot] [PATCH v2] Add support for IDS8313 boards Sergej.Stepanov at ids.de
2011-09-20 10:46 ` Heiko Schocher
2011-09-20 11:24 ` Wolfgang Denk
2011-09-20 11:24 ` Jason
     [not found] ` <4206182445660643B9AEB8D4E55BBD0A153BAC9965@HERMES2>
2011-11-03 20:31   ` [U-Boot] [PATCH v3 1/3] ids8313: add " Kim Phillips
2011-11-03 22:09     ` Kim Phillips

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