* [Qemu-devel] [PULL 0/4] pull: omap patches
@ 2011-09-23 11:46 Peter Maydell
2011-09-23 11:46 ` [Qemu-devel] [PATCH 1/4] omap_intc: Use MemoryRegion API Peter Maydell
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Peter Maydell @ 2011-09-23 11:46 UTC (permalink / raw)
To: Anthony Liguori, qemu-devel
This is a small pullreq for the couple of outstanding OMAP patches,
which I have now rebased following the landing of Avi's memoryregion
batch which touched omap1.c. I've also included the MAINTAINERS file
update. Please pull.
Thanks
-- PMM
The following changes since commit 7e36b264ce524bc60b7b71dd45c05af767ceff2b:
hw/omap_gpmc: Modify correct field when writing IRQSTATUS register (2011-09-23 08:36:58 +0200)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git omap-for-upstream
Peter Maydell (4):
omap_intc: Use MemoryRegion API
omap_intc: Qdevify
hw/omap1: Wire up GPIO clock
MAINTAINERS: claim maintainership for the OMAP devices
MAINTAINERS | 5 ++
hw/nseries.c | 4 +-
hw/omap.h | 21 +-------
hw/omap1.c | 142 ++++++++++++++++++++++++++++------------------
hw/omap2.c | 92 +++++++++++++++++------------
hw/omap_intc.c | 175 +++++++++++++++++++++++++++++++------------------------
6 files changed, 249 insertions(+), 190 deletions(-)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 1/4] omap_intc: Use MemoryRegion API
2011-09-23 11:46 [Qemu-devel] [PULL 0/4] pull: omap patches Peter Maydell
@ 2011-09-23 11:46 ` Peter Maydell
2011-09-23 11:46 ` [Qemu-devel] [PATCH 2/4] omap_intc: Qdevify Peter Maydell
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2011-09-23 11:46 UTC (permalink / raw)
To: Anthony Liguori, qemu-devel
Convert omap_intc to use the MemoryRegion API
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/omap_intc.c | 64 ++++++++++++++++++++++++++-----------------------------
1 files changed, 30 insertions(+), 34 deletions(-)
diff --git a/hw/omap_intc.c b/hw/omap_intc.c
index f1f570e..38637c6 100644
--- a/hw/omap_intc.c
+++ b/hw/omap_intc.c
@@ -19,6 +19,7 @@
*/
#include "hw.h"
#include "omap.h"
+#include "exec-memory.h"
/* Interrupt Handlers */
struct omap_intr_handler_bank_s {
@@ -34,6 +35,7 @@ struct omap_intr_handler_bank_s {
struct omap_intr_handler_s {
qemu_irq *pins;
qemu_irq parent_intr[2];
+ MemoryRegion mmio;
unsigned char nbanks;
int level_only;
@@ -142,7 +144,8 @@ static void omap_set_intr_noedge(void *opaque, int irq, int req)
bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
}
-static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_inth_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int i, offset = addr;
@@ -220,7 +223,7 @@ static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
}
static void omap_inth_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int i, offset = addr;
@@ -312,16 +315,14 @@ static void omap_inth_write(void *opaque, target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc * const omap_inth_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_inth_read,
-};
-
-static CPUWriteMemoryFunc * const omap_inth_writefn[] = {
- omap_inth_write,
- omap_inth_write,
- omap_inth_write,
+static const MemoryRegionOps omap_inth_mem_ops = {
+ .read = omap_inth_read,
+ .write = omap_inth_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
void omap_inth_reset(struct omap_intr_handler_s *s)
@@ -356,7 +357,6 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
unsigned long size, unsigned char nbanks, qemu_irq **pins,
qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
{
- int iomemtype;
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
g_malloc0(sizeof(struct omap_intr_handler_s) +
sizeof(struct omap_intr_handler_bank_s) * nbanks);
@@ -368,16 +368,16 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
if (pins)
*pins = s->pins;
- omap_inth_reset(s);
+ memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s, "omap-intc", size);
+ memory_region_add_subregion(get_system_memory(), base, &s->mmio);
- iomemtype = cpu_register_io_memory(omap_inth_readfn,
- omap_inth_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, size, iomemtype);
+ omap_inth_reset(s);
return s;
}
-static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int offset = addr;
@@ -455,7 +455,7 @@ static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
}
static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int offset = addr;
@@ -558,16 +558,14 @@ static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc * const omap2_inth_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap2_inth_read,
-};
-
-static CPUWriteMemoryFunc * const omap2_inth_writefn[] = {
- omap2_inth_write,
- omap2_inth_write,
- omap2_inth_write,
+static const MemoryRegionOps omap2_inth_mem_ops = {
+ .read = omap2_inth_read,
+ .write = omap2_inth_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
@@ -575,7 +573,6 @@ struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
qemu_irq parent_irq, qemu_irq parent_fiq,
omap_clk fclk, omap_clk iclk)
{
- int iomemtype;
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
g_malloc0(sizeof(struct omap_intr_handler_s) +
sizeof(struct omap_intr_handler_bank_s) * nbanks);
@@ -588,11 +585,10 @@ struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
if (pins)
*pins = s->pins;
- omap_inth_reset(s);
+ memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s, "omap2-intc", size);
+ memory_region_add_subregion(get_system_memory(), base, &s->mmio);
- iomemtype = cpu_register_io_memory(omap2_inth_readfn,
- omap2_inth_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, size, iomemtype);
+ omap_inth_reset(s);
return s;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 2/4] omap_intc: Qdevify
2011-09-23 11:46 [Qemu-devel] [PULL 0/4] pull: omap patches Peter Maydell
2011-09-23 11:46 ` [Qemu-devel] [PATCH 1/4] omap_intc: Use MemoryRegion API Peter Maydell
@ 2011-09-23 11:46 ` Peter Maydell
2011-09-23 11:46 ` [Qemu-devel] [PATCH 3/4] hw/omap1: Wire up GPIO clock Peter Maydell
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2011-09-23 11:46 UTC (permalink / raw)
To: Anthony Liguori, qemu-devel
Convert the omap_intc devices to qdev. This includes adding
a 'revision' property which will be needed for omap3.
The bulk of this patch is the replacement of "s->irq[x][y]"
with "qdev_get_gpio_in(s->ih[x], y)" now that the interrupt
controller exposes its input lines as qdev gpio inputs.
The devices are named "omap-intc" and "omap2-intc", following
the filename and the OMAP2/3 hardware names, although some
internal functions are still named "omap_inth_*".
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/nseries.c | 4 +-
hw/omap.h | 21 +--------
hw/omap1.c | 141 ++++++++++++++++++++++++++++++++++----------------------
hw/omap2.c | 92 +++++++++++++++++++++---------------
hw/omap_intc.c | 125 ++++++++++++++++++++++++++++++-------------------
5 files changed, 220 insertions(+), 163 deletions(-)
diff --git a/hw/nseries.c b/hw/nseries.c
index af287dd..eb99143 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -199,7 +199,9 @@ static void n8x0_i2c_setup(struct n800_s *s)
/* Attach a menelaus PM chip */
dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR);
- qdev_connect_gpio_out(dev, 3, s->cpu->irq[0][OMAP_INT_24XX_SYS_NIRQ]);
+ qdev_connect_gpio_out(dev, 3,
+ qdev_get_gpio_in(s->cpu->ih[0],
+ OMAP_INT_24XX_SYS_NIRQ));
/* Attach a TMP105 PM chip (A0 wired to ground) */
dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR);
diff --git a/hw/omap.h b/hw/omap.h
index 0260cc0..cc09a3c 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -99,18 +99,6 @@ target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
CPUWriteMemoryFunc * const *mem_write, void *opaque);
-/* OMAP interrupt controller */
-struct omap_intr_handler_s;
-struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
- unsigned long size, unsigned char nbanks, qemu_irq **pins,
- qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
-struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
- int size, int nbanks, qemu_irq **pins,
- qemu_irq parent_irq, qemu_irq parent_fiq,
- omap_clk fclk, omap_clk iclk);
-void omap_inth_reset(struct omap_intr_handler_s *s);
-qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n);
-
/* OMAP2 SDRAM controller */
struct omap_sdrc_s;
struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
@@ -692,9 +680,6 @@ struct uWireSlave {
void *opaque;
};
struct omap_uwire_s;
-struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
- qemu_irq *irq, qemu_irq dma, omap_clk clk);
void omap_uwire_attach(struct omap_uwire_s *s,
uWireSlave *slave, int chipselect);
@@ -732,9 +717,6 @@ struct I2SCodec {
} in, out;
};
struct omap_mcbsp_s;
-struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
- qemu_irq *irq, qemu_irq *dma, omap_clk clk);
void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
void omap_tap_init(struct omap_target_agent_s *ta,
@@ -823,7 +805,6 @@ struct omap_mpu_state_s {
CPUState *env;
- qemu_irq *irq[2];
qemu_irq *drq;
qemu_irq wakeup;
@@ -896,7 +877,7 @@ struct omap_mpu_state_s {
struct omap_lpg_s *led[2];
/* MPU private TIPB peripherals */
- struct omap_intr_handler_s *ih[2];
+ DeviceState *ih[2];
struct soc_dma_s *dma;
diff --git a/hw/omap1.c b/hw/omap1.c
index f747321..4bf88e8 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -524,7 +524,7 @@ static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
case 0x14: /* IT_STATUS */
ret = s->ulpd_pm_regs[addr >> 2];
s->ulpd_pm_regs[addr >> 2] = 0;
- qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
+ qemu_irq_lower(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
return ret;
case 0x18: /* Reserved */
@@ -625,7 +625,7 @@ static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
- qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
+ qemu_irq_raise(qdev_get_gpio_in(s->ih[1], OMAP_INT_GAUGE_32K));
}
}
s->ulpd_pm_regs[addr >> 2] = value;
@@ -2257,15 +2257,17 @@ static void omap_uwire_reset(struct omap_uwire_s *s)
s->setup[4] = 0;
}
-struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
- qemu_irq *irq, qemu_irq dma, omap_clk clk)
+static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
+ qemu_irq txirq, qemu_irq rxirq,
+ qemu_irq dma,
+ omap_clk clk)
{
struct omap_uwire_s *s = (struct omap_uwire_s *)
g_malloc0(sizeof(struct omap_uwire_s));
- s->txirq = irq[0];
- s->rxirq = irq[1];
+ s->txirq = txirq;
+ s->rxirq = rxirq;
s->txdrq = dma;
omap_uwire_reset(s);
@@ -2873,14 +2875,15 @@ static void omap_rtc_reset(struct omap_rtc_s *s)
}
static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
- qemu_irq *irq, omap_clk clk)
+ target_phys_addr_t base,
+ qemu_irq timerirq, qemu_irq alarmirq,
+ omap_clk clk)
{
struct omap_rtc_s *s = (struct omap_rtc_s *)
g_malloc0(sizeof(struct omap_rtc_s));
- s->irq = irq[0];
- s->alarm = irq[1];
+ s->irq = timerirq;
+ s->alarm = alarmirq;
s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s);
omap_rtc_reset(s);
@@ -3402,15 +3405,16 @@ static void omap_mcbsp_reset(struct omap_mcbsp_s *s)
qemu_del_timer(s->sink_timer);
}
-struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
- qemu_irq *irq, qemu_irq *dma, omap_clk clk)
+static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
+ target_phys_addr_t base,
+ qemu_irq txirq, qemu_irq rxirq,
+ qemu_irq *dma, omap_clk clk)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *)
g_malloc0(sizeof(struct omap_mcbsp_s));
- s->txirq = irq[0];
- s->rxirq = irq[1];
+ s->txirq = txirq;
+ s->rxirq = rxirq;
s->txdrq = dma[0];
s->rxdrq = dma[1];
s->sink_timer = qemu_new_timer_ns(vm_clock, omap_mcbsp_sink_tick, s);
@@ -3642,8 +3646,6 @@ static void omap1_mpu_reset(void *opaque)
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
- omap_inth_reset(mpu->ih[0]);
- omap_inth_reset(mpu->ih[1]);
omap_dma_reset(mpu->dma);
omap_mpu_timer_reset(mpu->timer[0]);
omap_mpu_timer_reset(mpu->timer[1]);
@@ -3796,6 +3798,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
qemu_irq *cpu_irq;
qemu_irq dma_irqs[6];
DriveInfo *dinfo;
+ SysBusDevice *busdev;
if (!core)
core = "ti925t";
@@ -3824,17 +3827,30 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
cpu_irq = arm_pic_init_cpu(s->env);
- s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0],
- cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
- omap_findclk(s, "arminth_ck"));
- s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1],
- omap_inth_get_pin(s->ih[0], OMAP_INT_15XX_IH2_IRQ),
- NULL, omap_findclk(s, "arminth_ck"));
-
- for (i = 0; i < 6; i ++)
- dma_irqs[i] =
- s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr];
- s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD],
+ s->ih[0] = qdev_create(NULL, "omap-intc");
+ qdev_prop_set_uint32(s->ih[0], "size", 0x100);
+ qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck"));
+ qdev_init_nofail(s->ih[0]);
+ busdev = sysbus_from_qdev(s->ih[0]);
+ sysbus_connect_irq(busdev, 0, cpu_irq[ARM_PIC_CPU_IRQ]);
+ sysbus_connect_irq(busdev, 1, cpu_irq[ARM_PIC_CPU_FIQ]);
+ sysbus_mmio_map(busdev, 0, 0xfffecb00);
+ s->ih[1] = qdev_create(NULL, "omap-intc");
+ qdev_prop_set_uint32(s->ih[1], "size", 0x800);
+ qdev_prop_set_ptr(s->ih[1], "clk", omap_findclk(s, "arminth_ck"));
+ qdev_init_nofail(s->ih[1]);
+ busdev = sysbus_from_qdev(s->ih[1]);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_15XX_IH2_IRQ));
+ /* The second interrupt controller's FIQ output is not wired up */
+ sysbus_mmio_map(busdev, 0, 0xfffe0000);
+
+ for (i = 0; i < 6; i++) {
+ dma_irqs[i] = qdev_get_gpio_in(s->ih[omap1_dma_irq_map[i].ih],
+ omap1_dma_irq_map[i].intr);
+ }
+ s->dma = omap_dma_init(0xfffed800, dma_irqs,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_DMA_LCD),
s, omap_findclk(s, "dma_ck"), omap_dma_3_1);
s->port[emiff ].addr_valid = omap_validate_emiff_addr;
@@ -3851,25 +3867,27 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
OMAP_IMIF_BASE, s->sram_size);
s->timer[0] = omap_mpu_timer_init(system_memory, 0xfffec500,
- s->irq[0][OMAP_INT_TIMER1],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER1),
omap_findclk(s, "mputim_ck"));
s->timer[1] = omap_mpu_timer_init(system_memory, 0xfffec600,
- s->irq[0][OMAP_INT_TIMER2],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER2),
omap_findclk(s, "mputim_ck"));
s->timer[2] = omap_mpu_timer_init(system_memory, 0xfffec700,
- s->irq[0][OMAP_INT_TIMER3],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_TIMER3),
omap_findclk(s, "mputim_ck"));
s->wdt = omap_wd_timer_init(system_memory, 0xfffec800,
- s->irq[0][OMAP_INT_WD_TIMER],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_WD_TIMER),
omap_findclk(s, "armwdt_ck"));
s->os_timer = omap_os_timer_init(system_memory, 0xfffb9000,
- s->irq[1][OMAP_INT_OS_TIMER],
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_OS_TIMER),
omap_findclk(s, "clk32-kHz"));
- s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
- omap_dma_get_lcdch(s->dma), omap_findclk(s, "lcd_ck"));
+ s->lcd = omap_lcdc_init(0xfffec000,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_LCD_CTRL),
+ omap_dma_get_lcdch(s->dma),
+ omap_findclk(s, "lcd_ck"));
omap_ulpd_pm_init(system_memory, 0xfffe0800, s);
omap_pin_cfg_init(system_memory, 0xfffe1000, s);
@@ -3878,27 +3896,30 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
omap_mpui_init(system_memory, 0xfffec900, s);
s->private_tipb = omap_tipb_bridge_init(system_memory, 0xfffeca00,
- s->irq[0][OMAP_INT_BRIDGE_PRIV],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PRIV),
omap_findclk(s, "tipb_ck"));
s->public_tipb = omap_tipb_bridge_init(system_memory, 0xfffed300,
- s->irq[0][OMAP_INT_BRIDGE_PUB],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_BRIDGE_PUB),
omap_findclk(s, "tipb_ck"));
omap_tcmi_init(system_memory, 0xfffecc00, s);
- s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
+ s->uart[0] = omap_uart_init(0xfffb0000,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_UART1),
omap_findclk(s, "uart1_ck"),
omap_findclk(s, "uart1_ck"),
s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX],
"uart1",
serial_hds[0]);
- s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
+ s->uart[1] = omap_uart_init(0xfffb0800,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2),
omap_findclk(s, "uart2_ck"),
omap_findclk(s, "uart2_ck"),
s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX],
"uart2",
serial_hds[0] ? serial_hds[1] : NULL);
- s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3],
+ s->uart[2] = omap_uart_init(0xfffb9800,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3),
omap_findclk(s, "uart3_ck"),
omap_findclk(s, "uart3_ck"),
s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX],
@@ -3918,42 +3939,52 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
exit(1);
}
s->mmc = omap_mmc_init(0xfffb7800, dinfo->bdrv,
- s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX],
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_OQN),
+ &s->drq[OMAP_DMA_MMC_TX],
omap_findclk(s, "mmc_ck"));
s->mpuio = omap_mpuio_init(system_memory, 0xfffb5000,
- s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO],
- s->wakeup, omap_findclk(s, "clk32-kHz"));
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_KEYBOARD),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_MPUIO),
+ s->wakeup, omap_findclk(s, "clk32-kHz"));
s->gpio = qdev_create(NULL, "omap-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
qdev_init_nofail(s->gpio);
sysbus_connect_irq(sysbus_from_qdev(s->gpio), 0,
- s->irq[0][OMAP_INT_GPIO_BANK1]);
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
sysbus_mmio_map(sysbus_from_qdev(s->gpio), 0, 0xfffce000);
- s->microwire = omap_uwire_init(system_memory,
- 0xfffb3000, &s->irq[1][OMAP_INT_uWireTX],
+ s->microwire = omap_uwire_init(system_memory, 0xfffb3000,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireTX),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX),
s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
omap_pwl_init(system_memory, 0xfffb5800, s, omap_findclk(s, "armxor_ck"));
omap_pwt_init(system_memory, 0xfffb6000, s, omap_findclk(s, "armxor_ck"));
- s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C],
+ s->i2c[0] = omap_i2c_init(0xfffb3800,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C),
&s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
- &s->irq[1][OMAP_INT_RTC_TIMER],
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_ALARM),
omap_findclk(s, "clk32-kHz"));
- s->mcbsp1 = omap_mcbsp_init(system_memory,
- 0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX],
+ s->mcbsp1 = omap_mcbsp_init(system_memory, 0xfffb1800,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1TX),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP1RX),
&s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck"));
- s->mcbsp2 = omap_mcbsp_init(system_memory,
- 0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX],
+ s->mcbsp2 = omap_mcbsp_init(system_memory, 0xfffb1000,
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_310_McBSP2_TX),
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_310_McBSP2_RX),
&s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck"));
- s->mcbsp3 = omap_mcbsp_init(system_memory,
- 0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX],
+ s->mcbsp3 = omap_mcbsp_init(system_memory, 0xfffb7000,
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3TX),
+ qdev_get_gpio_in(s->ih[1], OMAP_INT_McBSP3RX),
&s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck"));
s->led[0] = omap_lpg_init(system_memory,
diff --git a/hw/omap2.c b/hw/omap2.c
index 3d529ce..838c32f 100644
--- a/hw/omap2.c
+++ b/hw/omap2.c
@@ -2180,7 +2180,6 @@ static void omap2_mpu_reset(void *opaque)
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
- omap_inth_reset(mpu->ih[0]);
omap_dma_reset(mpu->dma);
omap_prcm_reset(mpu->prcm);
omap_sysctl_reset(mpu->sysc);
@@ -2264,20 +2263,27 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
/* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
cpu_irq = arm_pic_init_cpu(s->env);
- s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
- cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
- omap_findclk(s, "mpu_intc_fclk"),
- omap_findclk(s, "mpu_intc_iclk"));
-
+ s->ih[0] = qdev_create(NULL, "omap2-intc");
+ qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
+ qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk"));
+ qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk"));
+ qdev_init_nofail(s->ih[0]);
+ busdev = sysbus_from_qdev(s->ih[0]);
+ sysbus_connect_irq(busdev, 0, cpu_irq[ARM_PIC_CPU_IRQ]);
+ sysbus_connect_irq(busdev, 1, cpu_irq[ARM_PIC_CPU_FIQ]);
+ sysbus_mmio_map(busdev, 0, 0x480fe000);
s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
- s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_PRCM_MPU_IRQ),
+ NULL, NULL, s);
s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
omap_findclk(s, "omapctrl_iclk"), s);
- for (i = 0; i < 4; i ++)
- dma_irqs[i] =
- s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
+ for (i = 0; i < 4; i++) {
+ dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih],
+ omap2_dma_irq_map[i].intr);
+ }
s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
omap_findclk(s, "sdma_iclk"),
omap_findclk(s, "sdma_fclk"));
@@ -2290,7 +2296,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
OMAP2_SRAM_BASE, s->sram_size);
s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
- s->irq[0][OMAP_INT_24XX_UART1_IRQ],
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_UART1_IRQ),
omap_findclk(s, "uart1_fclk"),
omap_findclk(s, "uart1_iclk"),
s->drq[OMAP24XX_DMA_UART1_TX],
@@ -2298,7 +2305,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
"uart1",
serial_hds[0]);
s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
- s->irq[0][OMAP_INT_24XX_UART2_IRQ],
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_UART2_IRQ),
omap_findclk(s, "uart2_fclk"),
omap_findclk(s, "uart2_iclk"),
s->drq[OMAP24XX_DMA_UART2_TX],
@@ -2306,7 +2314,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
"uart2",
serial_hds[0] ? serial_hds[1] : NULL);
s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
- s->irq[0][OMAP_INT_24XX_UART3_IRQ],
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_UART3_IRQ),
omap_findclk(s, "uart3_fclk"),
omap_findclk(s, "uart3_iclk"),
s->drq[OMAP24XX_DMA_UART3_TX],
@@ -2315,51 +2324,51 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
- s->irq[0][OMAP_INT_24XX_GPTIMER1],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1),
omap_findclk(s, "wu_gpt1_clk"),
omap_findclk(s, "wu_l4_iclk"));
s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
- s->irq[0][OMAP_INT_24XX_GPTIMER2],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2),
omap_findclk(s, "core_gpt2_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
- s->irq[0][OMAP_INT_24XX_GPTIMER3],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3),
omap_findclk(s, "core_gpt3_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
- s->irq[0][OMAP_INT_24XX_GPTIMER4],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4),
omap_findclk(s, "core_gpt4_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
- s->irq[0][OMAP_INT_24XX_GPTIMER5],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5),
omap_findclk(s, "core_gpt5_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
- s->irq[0][OMAP_INT_24XX_GPTIMER6],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6),
omap_findclk(s, "core_gpt6_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
- s->irq[0][OMAP_INT_24XX_GPTIMER7],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7),
omap_findclk(s, "core_gpt7_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
- s->irq[0][OMAP_INT_24XX_GPTIMER8],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8),
omap_findclk(s, "core_gpt8_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
- s->irq[0][OMAP_INT_24XX_GPTIMER9],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9),
omap_findclk(s, "core_gpt9_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
- s->irq[0][OMAP_INT_24XX_GPTIMER10],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10),
omap_findclk(s, "core_gpt10_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
- s->irq[0][OMAP_INT_24XX_GPTIMER11],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11),
omap_findclk(s, "core_gpt11_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
- s->irq[0][OMAP_INT_24XX_GPTIMER12],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12),
omap_findclk(s, "core_gpt12_clk"),
omap_findclk(s, "core_l4_iclk"));
@@ -2370,12 +2379,12 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
omap_findclk(s, "core_l4_iclk"));
s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
- s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ),
&s->drq[OMAP24XX_DMA_I2C1_TX],
omap_findclk(s, "i2c1.fclk"),
omap_findclk(s, "i2c1.iclk"));
s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
- s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ),
&s->drq[OMAP24XX_DMA_I2C2_TX],
omap_findclk(s, "i2c2.fclk"),
omap_findclk(s, "i2c2.iclk"));
@@ -2392,10 +2401,14 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
}
qdev_init_nofail(s->gpio);
busdev = sysbus_from_qdev(s->gpio);
- sysbus_connect_irq(busdev, 0, s->irq[0][OMAP_INT_24XX_GPIO_BANK1]);
- sysbus_connect_irq(busdev, 3, s->irq[0][OMAP_INT_24XX_GPIO_BANK2]);
- sysbus_connect_irq(busdev, 6, s->irq[0][OMAP_INT_24XX_GPIO_BANK3]);
- sysbus_connect_irq(busdev, 9, s->irq[0][OMAP_INT_24XX_GPIO_BANK4]);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
+ sysbus_connect_irq(busdev, 3,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2));
+ sysbus_connect_irq(busdev, 6,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3));
+ sysbus_connect_irq(busdev, 9,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4));
ta = omap_l4ta(s->l4, 3);
sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1));
sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0));
@@ -2404,7 +2417,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
s->sdrc = omap_sdrc_init(0x68009000);
- s->gpmc = omap_gpmc_init(s, 0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ],
+ s->gpmc = omap_gpmc_init(s, 0x6800a000,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ),
s->drq[OMAP24XX_DMA_GPMC]);
dinfo = drive_get(IF_SD, 0, 0);
@@ -2413,36 +2427,38 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
exit(1);
}
s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), dinfo->bdrv,
- s->irq[0][OMAP_INT_24XX_MMC_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ),
&s->drq[OMAP24XX_DMA_MMC1_TX],
omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
- s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ),
&s->drq[OMAP24XX_DMA_SPI1_TX0],
omap_findclk(s, "spi1_fclk"),
omap_findclk(s, "spi1_iclk"));
s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
- s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ),
&s->drq[OMAP24XX_DMA_SPI2_TX0],
omap_findclk(s, "spi2_fclk"),
omap_findclk(s, "spi2_iclk"));
s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
/* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
- s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
+ s->drq[OMAP24XX_DMA_DSS],
omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
omap_findclk(s, "dss_54m_clk"),
omap_findclk(s, "dss_l3_iclk"),
omap_findclk(s, "dss_l4_iclk"));
omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
- s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI),
+ omap_findclk(s, "emul_ck"),
serial_hds[0] && serial_hds[1] && serial_hds[2] ?
serial_hds[3] : NULL);
s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
- s->irq[0][OMAP_INT_24XX_EAC_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ),
/* Ten consecutive lines */
&s->drq[OMAP24XX_DMA_EAC_AC_RD],
omap_findclk(s, "func_96m_clk"),
diff --git a/hw/omap_intc.c b/hw/omap_intc.c
index 38637c6..0f7fd9d 100644
--- a/hw/omap_intc.c
+++ b/hw/omap_intc.c
@@ -19,7 +19,7 @@
*/
#include "hw.h"
#include "omap.h"
-#include "exec-memory.h"
+#include "sysbus.h"
/* Interrupt Handlers */
struct omap_intr_handler_bank_s {
@@ -33,25 +33,26 @@ struct omap_intr_handler_bank_s {
};
struct omap_intr_handler_s {
+ SysBusDevice busdev;
qemu_irq *pins;
qemu_irq parent_intr[2];
MemoryRegion mmio;
+ void *iclk;
+ void *fclk;
unsigned char nbanks;
int level_only;
+ uint32_t size;
+
+ uint8_t revision;
/* state */
uint32_t new_agr[2];
int sir_intr[2];
int autoidle;
uint32_t mask;
- struct omap_intr_handler_bank_s bank[];
+ struct omap_intr_handler_bank_s bank[3];
};
-inline qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n)
-{
- return s->pins[n];
-}
-
static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
{
int i, j, sir_intr, p_intr, p, f;
@@ -325,8 +326,10 @@ static const MemoryRegionOps omap_inth_mem_ops = {
},
};
-void omap_inth_reset(struct omap_intr_handler_s *s)
+static void omap_inth_reset(DeviceState *dev)
{
+ struct omap_intr_handler_s *s = FROM_SYSBUS(struct omap_intr_handler_s,
+ sysbus_from_qdev(dev));
int i;
for (i = 0; i < s->nbanks; ++i){
@@ -353,29 +356,35 @@ void omap_inth_reset(struct omap_intr_handler_s *s)
qemu_set_irq(s->parent_intr[1], 0);
}
-struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
- unsigned long size, unsigned char nbanks, qemu_irq **pins,
- qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
+static int omap_intc_init(SysBusDevice *dev)
{
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
- g_malloc0(sizeof(struct omap_intr_handler_s) +
- sizeof(struct omap_intr_handler_bank_s) * nbanks);
-
- s->parent_intr[0] = parent_irq;
- s->parent_intr[1] = parent_fiq;
- s->nbanks = nbanks;
- s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
- if (pins)
- *pins = s->pins;
-
- memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s, "omap-intc", size);
- memory_region_add_subregion(get_system_memory(), base, &s->mmio);
-
- omap_inth_reset(s);
-
- return s;
+ struct omap_intr_handler_s *s;
+ s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
+ if (!s->iclk) {
+ hw_error("omap-intc: clk not connected\n");
+ }
+ s->nbanks = 1;
+ sysbus_init_irq(dev, &s->parent_intr[0]);
+ sysbus_init_irq(dev, &s->parent_intr[1]);
+ qdev_init_gpio_in(&dev->qdev, omap_set_intr, s->nbanks * 32);
+ memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s,
+ "omap-intc", s->size);
+ sysbus_init_mmio_region(dev, &s->mmio);
+ return 0;
}
+static SysBusDeviceInfo omap_intc_info = {
+ .init = omap_intc_init,
+ .qdev.name = "omap-intc",
+ .qdev.size = sizeof(struct omap_intr_handler_s),
+ .qdev.reset = omap_inth_reset,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
+ DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
+ DEFINE_PROP_END_OF_LIST()
+ }
+};
+
static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
@@ -394,7 +403,7 @@ static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
switch (offset) {
case 0x00: /* INTC_REVISION */
- return 0x21;
+ return s->revision;
case 0x10: /* INTC_SYSCONFIG */
return (s->autoidle >> 2) & 1;
@@ -475,7 +484,7 @@ static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
s->autoidle &= 4;
s->autoidle |= (value & 1) << 2;
if (value & 2) /* SOFTRESET */
- omap_inth_reset(s);
+ omap_inth_reset(&s->busdev.qdev);
return;
case 0x48: /* INTC_CONTROL */
@@ -568,27 +577,45 @@ static const MemoryRegionOps omap2_inth_mem_ops = {
},
};
-struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
- int size, int nbanks, qemu_irq **pins,
- qemu_irq parent_irq, qemu_irq parent_fiq,
- omap_clk fclk, omap_clk iclk)
+static int omap2_intc_init(SysBusDevice *dev)
{
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
- g_malloc0(sizeof(struct omap_intr_handler_s) +
- sizeof(struct omap_intr_handler_bank_s) * nbanks);
-
- s->parent_intr[0] = parent_irq;
- s->parent_intr[1] = parent_fiq;
- s->nbanks = nbanks;
+ struct omap_intr_handler_s *s;
+ s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
+ if (!s->iclk) {
+ hw_error("omap2-intc: iclk not connected\n");
+ }
+ if (!s->fclk) {
+ hw_error("omap2-intc: fclk not connected\n");
+ }
s->level_only = 1;
- s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
- if (pins)
- *pins = s->pins;
-
- memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s, "omap2-intc", size);
- memory_region_add_subregion(get_system_memory(), base, &s->mmio);
+ s->nbanks = 3;
+ sysbus_init_irq(dev, &s->parent_intr[0]);
+ sysbus_init_irq(dev, &s->parent_intr[1]);
+ qdev_init_gpio_in(&dev->qdev, omap_set_intr_noedge, s->nbanks * 32);
+ memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s,
+ "omap2-intc", 0x1000);
+ sysbus_init_mmio_region(dev, &s->mmio);
+ return 0;
+}
- omap_inth_reset(s);
+static SysBusDeviceInfo omap2_intc_info = {
+ .init = omap2_intc_init,
+ .qdev.name = "omap2-intc",
+ .qdev.size = sizeof(struct omap_intr_handler_s),
+ .qdev.reset = omap_inth_reset,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
+ revision, 0x21),
+ DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
+ DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
+ DEFINE_PROP_END_OF_LIST()
+ }
+};
- return s;
+static void omap_intc_register_device(void)
+{
+ sysbus_register_withprop(&omap_intc_info);
+ sysbus_register_withprop(&omap2_intc_info);
}
+
+device_init(omap_intc_register_device)
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 3/4] hw/omap1: Wire up GPIO clock
2011-09-23 11:46 [Qemu-devel] [PULL 0/4] pull: omap patches Peter Maydell
2011-09-23 11:46 ` [Qemu-devel] [PATCH 1/4] omap_intc: Use MemoryRegion API Peter Maydell
2011-09-23 11:46 ` [Qemu-devel] [PATCH 2/4] omap_intc: Qdevify Peter Maydell
@ 2011-09-23 11:46 ` Peter Maydell
2011-09-23 11:46 ` [Qemu-devel] [PATCH 4/4] MAINTAINERS: claim maintainership for the OMAP devices Peter Maydell
2011-09-26 13:28 ` [Qemu-devel] [PULL 0/4] pull: omap patches Anthony Liguori
4 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2011-09-23 11:46 UTC (permalink / raw)
To: Anthony Liguori, qemu-devel
Wire up the OMAP1 GPIO clock -- this fixes a hw_error() on startup
with OMAP1 based machines (sx1, cheetah).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/omap1.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/omap1.c b/hw/omap1.c
index 4bf88e8..619812c 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -3950,6 +3950,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
s->gpio = qdev_create(NULL, "omap-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
+ qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck"));
qdev_init_nofail(s->gpio);
sysbus_connect_irq(sysbus_from_qdev(s->gpio), 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1));
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH 4/4] MAINTAINERS: claim maintainership for the OMAP devices
2011-09-23 11:46 [Qemu-devel] [PULL 0/4] pull: omap patches Peter Maydell
` (2 preceding siblings ...)
2011-09-23 11:46 ` [Qemu-devel] [PATCH 3/4] hw/omap1: Wire up GPIO clock Peter Maydell
@ 2011-09-23 11:46 ` Peter Maydell
2011-09-26 13:28 ` [Qemu-devel] [PULL 0/4] pull: omap patches Anthony Liguori
4 siblings, 0 replies; 6+ messages in thread
From: Peter Maydell @ 2011-09-23 11:46 UTC (permalink / raw)
To: Anthony Liguori, qemu-devel
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---
MAINTAINERS | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7c5ea87..5046dc9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -355,6 +355,11 @@ M: Kevin Wolf <kwolf@redhat.com>
S: Odd Fixes
F: hw/ide/
+OMAP
+M: Peter Maydell <peter.maydell@linaro.org>
+S: Maintained
+F: hw/omap*
+
PCI
M: Michael S. Tsirkin <mst@redhat.com>
S: Supported
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PULL 0/4] pull: omap patches
2011-09-23 11:46 [Qemu-devel] [PULL 0/4] pull: omap patches Peter Maydell
` (3 preceding siblings ...)
2011-09-23 11:46 ` [Qemu-devel] [PATCH 4/4] MAINTAINERS: claim maintainership for the OMAP devices Peter Maydell
@ 2011-09-26 13:28 ` Anthony Liguori
4 siblings, 0 replies; 6+ messages in thread
From: Anthony Liguori @ 2011-09-26 13:28 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
On 09/23/2011 06:46 AM, Peter Maydell wrote:
> This is a small pullreq for the couple of outstanding OMAP patches,
> which I have now rebased following the landing of Avi's memoryregion
> batch which touched omap1.c. I've also included the MAINTAINERS file
> update. Please pull.
>
> Thanks
> -- PMM
Pulled. Thanks.
Regards,
Anthony Liguori
>
>
> The following changes since commit 7e36b264ce524bc60b7b71dd45c05af767ceff2b:
>
> hw/omap_gpmc: Modify correct field when writing IRQSTATUS register (2011-09-23 08:36:58 +0200)
>
> are available in the git repository at:
> git://git.linaro.org/people/pmaydell/qemu-arm.git omap-for-upstream
>
> Peter Maydell (4):
> omap_intc: Use MemoryRegion API
> omap_intc: Qdevify
> hw/omap1: Wire up GPIO clock
> MAINTAINERS: claim maintainership for the OMAP devices
>
> MAINTAINERS | 5 ++
> hw/nseries.c | 4 +-
> hw/omap.h | 21 +-------
> hw/omap1.c | 142 ++++++++++++++++++++++++++++------------------
> hw/omap2.c | 92 +++++++++++++++++------------
> hw/omap_intc.c | 175 +++++++++++++++++++++++++++++++------------------------
> 6 files changed, 249 insertions(+), 190 deletions(-)
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2011-09-26 13:28 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-09-23 11:46 [Qemu-devel] [PULL 0/4] pull: omap patches Peter Maydell
2011-09-23 11:46 ` [Qemu-devel] [PATCH 1/4] omap_intc: Use MemoryRegion API Peter Maydell
2011-09-23 11:46 ` [Qemu-devel] [PATCH 2/4] omap_intc: Qdevify Peter Maydell
2011-09-23 11:46 ` [Qemu-devel] [PATCH 3/4] hw/omap1: Wire up GPIO clock Peter Maydell
2011-09-23 11:46 ` [Qemu-devel] [PATCH 4/4] MAINTAINERS: claim maintainership for the OMAP devices Peter Maydell
2011-09-26 13:28 ` [Qemu-devel] [PULL 0/4] pull: omap patches Anthony Liguori
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