From: Fabien Chouteau <chouteau@adacore.com>
To: Alexander Graf <agraf@suse.de>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH] Set an invalid-bits mask for each SPE instructions
Date: Fri, 07 Oct 2011 15:10:54 +0200 [thread overview]
Message-ID: <4E8EFA5E.4020101@adacore.com> (raw)
In-Reply-To: <4E8EF34F.3010309@suse.de>
On 07/10/2011 14:40, Alexander Graf wrote:
> On 09/28/2011 05:54 PM, Fabien Chouteau wrote:
>> SPE instructions are defined by pairs. Currently, the invalid-bits mask is set
>> for the first instruction, but the second one can have a different mask.
>>
>> example:
>> GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
>>
>> Signed-off-by: Fabien Chouteau<chouteau@adacore.com>
>
> It certainly doesn't make the code more ugly than it was before :). Applied to my local ppc-next branch. I take it that you verified all the invalid masks are sane.
>
Yes I checked all the masks so they should be OK.
> There are some lines exceeding 80 characters, but I'm fairly sure they did before too. So I'll let this slip through for the sake of readability.
>
For these kind of definition lists the 80 characters limit can result in
very awful code.
Regards,
--
Fabien Chouteau
prev parent reply other threads:[~2011-10-07 13:11 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-28 15:54 [Qemu-devel] [PATCH] Set an invalid-bits mask for each SPE instructions Fabien Chouteau
2011-10-06 14:41 ` Fabien Chouteau
2011-10-07 12:40 ` Alexander Graf
2011-10-07 13:10 ` Fabien Chouteau [this message]
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