* [U-Boot] [PATCH 2/8] MX35: add pins definition for UART3
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
@ 2011-09-16 9:46 ` Stefano Babic
2011-09-16 9:46 ` [U-Boot] [PATCH 3/8] MX35: add reset cause as provided by other i.MX Stefano Babic
` (10 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Stefano Babic @ 2011-09-16 9:46 UTC (permalink / raw)
To: u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
arch/arm/include/asm/arch-mx35/mx35_pins.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx35/mx35_pins.h b/arch/arm/include/asm/arch-mx35/mx35_pins.h
index 14669ff..3676e33 100644
--- a/arch/arm/include/asm/arch-mx35/mx35_pins.h
+++ b/arch/arm/include/asm/arch-mx35/mx35_pins.h
@@ -349,6 +349,9 @@ typedef enum iomux_pins {
MX35_PIN_FEC_TDATA2 = _MXC_BUILD_GPIO_PIN(2, 21, 0x31C, 0x780),
MX35_PIN_FEC_RDATA3 = _MXC_BUILD_GPIO_PIN(2, 22, 0x320, 0x784),
MX35_PIN_FEC_TDATA3 = _MXC_BUILD_GPIO_PIN(2, 23, 0x324, 0x788),
+
+ MX35_PIN_RTS2_UART3_RXD_MUX = _MXC_BUILD_NON_GPIO_PIN(0x1a0, 0x5e4),
+ MX35_PIN_CTS2_UART3_TXD_MUX = _MXC_BUILD_NON_GPIO_PIN(0x1a4, 0x5e8),
} iomux_pin_name_t;
#endif
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH 3/8] MX35: add reset cause as provided by other i.MX
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
2011-09-16 9:46 ` [U-Boot] [PATCH 2/8] MX35: add pins definition for UART3 Stefano Babic
@ 2011-09-16 9:46 ` Stefano Babic
2011-09-16 9:46 ` [U-Boot] [PATCH 4/8] MX35: factorize common assembly code Stefano Babic
` (9 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Stefano Babic @ 2011-09-16 9:46 UTC (permalink / raw)
To: u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
arch/arm/cpu/arm1136/mx35/generic.c | 31 +++++++++++++++++++++++++++++--
1 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index fcfaba5..951bccb 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -422,12 +422,39 @@ U_BOOT_CMD(
""
);
+static char *get_reset_cause(void)
+{
+ /* read RCSR register from CCM module */
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ u32 cause = readl(&ccm->rcsr) & 0x0F;
+
+ switch (cause) {
+ case 0x0000:
+ return "POR";
+ case 0x0002:
+ return "JTAG";
+ case 0x0004:
+ return "RST";
+ case 0x0008:
+ return "WDOG";
+ default:
+ return "unknown reset";
+ }
+}
+
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- printf("CPU: Freescale i.MX35 at %d MHz\n",
+ u32 srev = get_cpu_rev();
+
+ printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
+ (srev & 0xF0) >> 4, (srev & 0x0F),
get_mcu_main_clk() / 1000000);
- /* mxc_dump_clocks(); */
+
+ printf("Reset cause: %s\n", get_reset_cause());
+
return 0;
}
#endif
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH 4/8] MX35: factorize common assembly code
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
2011-09-16 9:46 ` [U-Boot] [PATCH 2/8] MX35: add pins definition for UART3 Stefano Babic
2011-09-16 9:46 ` [U-Boot] [PATCH 3/8] MX35: add reset cause as provided by other i.MX Stefano Babic
@ 2011-09-16 9:46 ` Stefano Babic
2011-09-16 9:46 ` [U-Boot] [PATCH 5/8] ARM: moved general function to arm/lib Stefano Babic
` (8 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Stefano Babic @ 2011-09-16 9:46 UTC (permalink / raw)
To: u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
arch/arm/include/asm/arch-mx35/lowlevel_macro.S | 140 +++++++++++++++++++++++
1 files changed, 140 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-mx35/lowlevel_macro.S
diff --git a/arch/arm/include/asm/arch-mx35/lowlevel_macro.S b/arch/arm/include/asm/arch-mx35/lowlevel_macro.S
new file mode 100644
index 0000000..05aa951
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx35/lowlevel_macro.S
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ */
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =AIPS_MPR_CONFIG
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x00]
+ str r1, [r0, #0x04]
+
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =AIPS_OPACR_CONFIG
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ str r1, [r0, #0x50]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x40]
+ str r1, [r0, #0x44]
+ str r1, [r0, #0x48]
+ str r1, [r0, #0x4C]
+ str r1, [r0, #0x50]
+.endm
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+ ldr r0, =MAX_BASE_ADDR
+ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+ ldr r1, =MAX_MPR_CONFIG
+ str r1, [r0, #0x000] /* for S0 */
+ str r1, [r0, #0x100] /* for S1 */
+ str r1, [r0, #0x200] /* for S2 */
+ str r1, [r0, #0x300] /* for S3 */
+ str r1, [r0, #0x400] /* for S4 */
+ /* SGPCR - always park on last master */
+ ldr r1, =MAX_SGPCR_CONFIG
+ str r1, [r0, #0x010] /* for S0 */
+ str r1, [r0, #0x110] /* for S1 */
+ str r1, [r0, #0x210] /* for S2 */
+ str r1, [r0, #0x310] /* for S3 */
+ str r1, [r0, #0x410] /* for S4 */
+ /* MGPCR - restore default values */
+ ldr r1, =MAX_MGPCR_CONFIG
+ str r1, [r0, #0x800] /* for M0 */
+ str r1, [r0, #0x900] /* for M1 */
+ str r1, [r0, #0xA00] /* for M2 */
+ str r1, [r0, #0xB00] /* for M3 */
+ str r1, [r0, #0xC00] /* for M4 */
+ str r1, [r0, #0xD00] /* for M5 */
+.endm
+
+/* M3IF setup */
+.macro init_m3if
+ /* Configure M3IF registers */
+ ldr r1, =M3IF_BASE_ADDR
+ /*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+ ldr r0, =M3IF_CONFIG
+ str r0, [r1] /* M3IF control reg */
+.endm
+
+.macro core_init
+ mrc 15, 0, r1, c1, c0, 0
+
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #7
+ mcr 15, 0, r0, c1, c0, 1
+ orr r1, r1, #(1<<11)
+
+ /* Set unaligned access enable */
+ orr r1, r1, #(1<<22)
+
+ /* Set low int latency enable */
+ orr r1, r1, #(1<<21)
+
+ mcr 15, 0, r1, c1, c0, 0
+
+ mov r0, #0
+
+ /* Set branch prediction enable */
+ mcr 15, 0, r0, c15, c2, 4
+
+ mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
+ mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+ /*
+ * initializes very early AIPS
+ * Then it also initializes Multi-Layer AHB Crossbar Switch,
+ * M3IF
+ * Also setup the Peripheral Port Remap register inside the core
+ */
+ ldr r0, =0x40000015 /* start from AIPS 2GB region */
+ mcr p15, 0, r0, c15, c2, 4
+.endm
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH 5/8] ARM: moved general function to arm/lib
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
` (2 preceding siblings ...)
2011-09-16 9:46 ` [U-Boot] [PATCH 4/8] MX35: factorize common assembly code Stefano Babic
@ 2011-09-16 9:46 ` Stefano Babic
2011-09-28 18:22 ` Stefano Babic
2011-10-06 21:30 ` Wolfgang Denk
2011-09-16 9:46 ` [U-Boot] [PATCH 6/8] I2C: added I2C-2 and I2C-3 to MX35 Stefano Babic
` (7 subsequent siblings)
11 siblings, 2 replies; 29+ messages in thread
From: Stefano Babic @ 2011-09-16 9:46 UTC (permalink / raw)
To: u-boot
Functions inside armv7/syslib can be used by other ARM
architectures, too. The file is added as part of
ARM library.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
---
arch/arm/cpu/armv7/Makefile | 2 -
arch/arm/cpu/armv7/syslib.c | 69 -------------------------------------------
arch/arm/lib/Makefile | 2 +
arch/arm/lib/syslib.c | 69 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 71 insertions(+), 71 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/syslib.c
create mode 100644 arch/arm/lib/syslib.c
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 92a5a96..5b7f1c7 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,8 +32,6 @@ COBJS += cache_v7.o
COBJS += cpu.o
endif
-COBJS += syslib.o
-
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
START := $(addprefix $(obj),$(START))
diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/cpu/armv7/syslib.c
deleted file mode 100644
index 84d17f0..0000000
--- a/arch/arm/cpu/armv7/syslib.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments, <www.ti.com>
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-/************************************************************
- * sdelay() - simple spin loop. Will be constant time as
- * its generally used in bypass conditions only. This
- * is necessary until timers are accessible.
- *
- * not inline to increase chances its in cache when called
- *************************************************************/
-void sdelay(unsigned long loops)
-{
- __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
- "bne 1b":"=r" (loops):"0"(loops));
-}
-
-/*****************************************************************
- * sr32 - clear & set a value in a bit range for a 32 bit address
- *****************************************************************/
-void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
-{
- u32 tmp, msk = 0;
- msk = 1 << num_bits;
- --msk;
- tmp = readl((u32)addr) & ~(msk << start_bit);
- tmp |= value << start_bit;
- writel(tmp, (u32)addr);
-}
-
-/*********************************************************************
- * wait_on_value() - common routine to allow waiting for changes in
- * volatile regs.
- *********************************************************************/
-u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
- u32 bound)
-{
- u32 i = 0, val;
- do {
- ++i;
- val = readl((u32)read_addr) & read_bit_mask;
- if (val == match_value)
- return 1;
- if (i == bound)
- return 0;
- } while (1);
-}
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 300c8fa..c966aa7 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -48,6 +48,8 @@ SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
endif
+COBJS-y += syslib.o
+
SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
$(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/arm/lib/syslib.c b/arch/arm/lib/syslib.c
new file mode 100644
index 0000000..84d17f0
--- /dev/null
+++ b/arch/arm/lib/syslib.c
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+/************************************************************
+ * sdelay() - simple spin loop. Will be constant time as
+ * its generally used in bypass conditions only. This
+ * is necessary until timers are accessible.
+ *
+ * not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*****************************************************************
+ * sr32 - clear & set a value in a bit range for a 32 bit address
+ *****************************************************************/
+void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
+{
+ u32 tmp, msk = 0;
+ msk = 1 << num_bits;
+ --msk;
+ tmp = readl((u32)addr) & ~(msk << start_bit);
+ tmp |= value << start_bit;
+ writel(tmp, (u32)addr);
+}
+
+/*********************************************************************
+ * wait_on_value() - common routine to allow waiting for changes in
+ * volatile regs.
+ *********************************************************************/
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+ u32 bound)
+{
+ u32 i = 0, val;
+ do {
+ ++i;
+ val = readl((u32)read_addr) & read_bit_mask;
+ if (val == match_value)
+ return 1;
+ if (i == bound)
+ return 0;
+ } while (1);
+}
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH 5/8] ARM: moved general function to arm/lib
2011-09-16 9:46 ` [U-Boot] [PATCH 5/8] ARM: moved general function to arm/lib Stefano Babic
@ 2011-09-28 18:22 ` Stefano Babic
2011-10-06 21:30 ` Wolfgang Denk
1 sibling, 0 replies; 29+ messages in thread
From: Stefano Babic @ 2011-09-28 18:22 UTC (permalink / raw)
To: u-boot
On 09/16/2011 11:46 AM, Stefano Babic wrote:
> Functions inside armv7/syslib can be used by other ARM
> architectures, too. The file is added as part of
> ARM library.
>
Hi Albert,
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
Any issue regarding this patch (code was not really changed, the files
are only moved to be available for other SOCs) ? I have some other
patches for i.MX that depend on this one.....
Thanks,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 29+ messages in thread
* [U-Boot] [PATCH 5/8] ARM: moved general function to arm/lib
2011-09-16 9:46 ` [U-Boot] [PATCH 5/8] ARM: moved general function to arm/lib Stefano Babic
2011-09-28 18:22 ` Stefano Babic
@ 2011-10-06 21:30 ` Wolfgang Denk
2011-10-06 22:11 ` stefano babic
1 sibling, 1 reply; 29+ messages in thread
From: Wolfgang Denk @ 2011-10-06 21:30 UTC (permalink / raw)
To: u-boot
Dear Stefano Babic,
In message <1316166383-11314-5-git-send-email-sbabic@denx.de> you wrote:
> Functions inside armv7/syslib can be used by other ARM
> architectures, too. The file is added as part of
> ARM library.
>
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
> ---
> arch/arm/cpu/armv7/Makefile | 2 -
> arch/arm/cpu/armv7/syslib.c | 69 -------------------------------------------
> arch/arm/lib/Makefile | 2 +
> arch/arm/lib/syslib.c | 69 +++++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 71 insertions(+), 71 deletions(-)
> delete mode 100644 arch/arm/cpu/armv7/syslib.c
> create mode 100644 arch/arm/lib/syslib.c
Checkpatch says:
total: 2 errors, 0 warnings, 85 lines checked
Please clean up and resubmit. Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The optimum committee has no members.
- Norman Augustine
^ permalink raw reply [flat|nested] 29+ messages in thread* [U-Boot] [PATCH 5/8] ARM: moved general function to arm/lib
2011-10-06 21:30 ` Wolfgang Denk
@ 2011-10-06 22:11 ` stefano babic
2011-10-06 22:25 ` Wolfgang Denk
0 siblings, 1 reply; 29+ messages in thread
From: stefano babic @ 2011-10-06 22:11 UTC (permalink / raw)
To: u-boot
Am 06/10/2011 23:30, schrieb Wolfgang Denk:
> Dear Stefano Babic,
>
> In message <1316166383-11314-5-git-send-email-sbabic@denx.de> you wrote:
>> Functions inside armv7/syslib can be used by other ARM
>> architectures, too. The file is added as part of
>> ARM library.
>>
>> Signed-off-by: Stefano Babic <sbabic@denx.de>
>> CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
>> ---
>> arch/arm/cpu/armv7/Makefile | 2 -
>> arch/arm/cpu/armv7/syslib.c | 69 -------------------------------------------
>> arch/arm/lib/Makefile | 2 +
>> arch/arm/lib/syslib.c | 69 +++++++++++++++++++++++++++++++++++++++++++
>> 4 files changed, 71 insertions(+), 71 deletions(-)
>> delete mode 100644 arch/arm/cpu/armv7/syslib.c
>> create mode 100644 arch/arm/lib/syslib.c
>
> Checkpatch says:
>
> total: 2 errors, 0 warnings, 85 lines checked
>
> Please clean up and resubmit. Thanks.
mmhhh..I do not know if this is correct. The patch is really only a "git
mv", an the original files are only moved. If I run checkpatch, I see:
ERROR: spaces required around that ':' (ctx:VxV)
#164: FILE: arch/arm/lib/syslib.c:37:
+ "bne 1b":"=r" (loops):"0"(loops));
^
ERROR: spaces required around that ':' (ctx:VxV)
#164: FILE: arch/arm/lib/syslib.c:37:
+ "bne 1b":"=r" (loops):"0"(loops));
^
total: 2 errors, 0 warnings, 85 lines checked
This is an assembly inline - are we sure we apply the same rules for C
and assembly ?
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 29+ messages in thread
* [U-Boot] [PATCH 5/8] ARM: moved general function to arm/lib
2011-10-06 22:11 ` stefano babic
@ 2011-10-06 22:25 ` Wolfgang Denk
0 siblings, 0 replies; 29+ messages in thread
From: Wolfgang Denk @ 2011-10-06 22:25 UTC (permalink / raw)
To: u-boot
Dear stefano babic,
In message <4E8E279B.8000405@denx.de> you wrote:
>
> >> arch/arm/cpu/armv7/Makefile | 2 -
> >> arch/arm/cpu/armv7/syslib.c | 69 -------------------------------------------
> >> arch/arm/lib/Makefile | 2 +
> >> arch/arm/lib/syslib.c | 69 +++++++++++++++++++++++++++++++++++++++++++
> >> 4 files changed, 71 insertions(+), 71 deletions(-)
> >> delete mode 100644 arch/arm/cpu/armv7/syslib.c
> >> create mode 100644 arch/arm/lib/syslib.c
> >
> > Checkpatch says:
> >
> > total: 2 errors, 0 warnings, 85 lines checked
> >
> > Please clean up and resubmit. Thanks.
>
> mmhhh..I do not know if this is correct. The patch is really only a "git
> mv", an the original files are only moved. If I run checkpatch, I see:
No, it's NOT a mv, it's a remove + add. The patch was not correctly
formatted. This should be fixed, then!
> ERROR: spaces required around that ':' (ctx:VxV)
> #164: FILE: arch/arm/lib/syslib.c:37:
> + "bne 1b":"=r" (loops):"0"(loops));
> ^
>
> ERROR: spaces required around that ':' (ctx:VxV)
> #164: FILE: arch/arm/lib/syslib.c:37:
> + "bne 1b":"=r" (loops):"0"(loops));
> ^
>
> total: 2 errors, 0 warnings, 85 lines checked
>
> This is an assembly inline - are we sure we apply the same rules for C
> and assembly ?
Guess you are right here. Sorry.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Doubt is a pain too lonely to know that faith is his twin brother.
- Kahlil Gibran
^ permalink raw reply [flat|nested] 29+ messages in thread
* [U-Boot] [PATCH 6/8] I2C: added I2C-2 and I2C-3 to MX35
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
` (3 preceding siblings ...)
2011-09-16 9:46 ` [U-Boot] [PATCH 5/8] ARM: moved general function to arm/lib Stefano Babic
@ 2011-09-16 9:46 ` Stefano Babic
2011-09-19 6:14 ` Heiko Schocher
2011-09-16 9:46 ` [U-Boot] [PATCH 7/8] MX35: Drop unnecessary prototypes from imx-regs.h Stefano Babic
` (6 subsequent siblings)
11 siblings, 1 reply; 29+ messages in thread
From: Stefano Babic @ 2011-09-16 9:46 UTC (permalink / raw)
To: u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Heiko Schocher <hs@denx.de>
---
drivers/i2c/mxc_i2c.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index ebde3c5..25c33eb 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -63,6 +63,10 @@
#define I2C_BASE I2C2_BASE_ADDR
#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
#define I2C_BASE I2C_BASE_ADDR
+#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
+#define I2C_BASE I2C2_BASE_ADDR
+#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
+#define I2C_BASE I2C3_BASE_ADDR
#else
#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
#endif
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH 7/8] MX35: Drop unnecessary prototypes from imx-regs.h
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
` (4 preceding siblings ...)
2011-09-16 9:46 ` [U-Boot] [PATCH 6/8] I2C: added I2C-2 and I2C-3 to MX35 Stefano Babic
@ 2011-09-16 9:46 ` Stefano Babic
2011-09-16 9:46 ` [U-Boot] [PATCH 8/8] MX35: add support for flea3 board Stefano Babic
` (5 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Stefano Babic @ 2011-09-16 9:46 UTC (permalink / raw)
To: u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
arch/arm/include/asm/arch-mx35/imx-regs.h | 4 ----
1 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
index 08fd2d5..038f0b6 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -325,9 +325,5 @@ struct esdc_regs {
#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
-extern unsigned int get_board_rev(void);
-extern int is_soc_rev(int rev);
-extern int sdhc_init(void);
-
#endif
#endif /* __ASM_ARCH_MX35_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH 8/8] MX35: add support for flea3 board
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
` (5 preceding siblings ...)
2011-09-16 9:46 ` [U-Boot] [PATCH 7/8] MX35: Drop unnecessary prototypes from imx-regs.h Stefano Babic
@ 2011-09-16 9:46 ` Stefano Babic
2011-09-16 11:48 ` Fabio Estevam
` (3 more replies)
2011-09-20 14:12 ` [U-Boot] [PATCH V3 " Stefano Babic
` (4 subsequent siblings)
11 siblings, 4 replies; 29+ messages in thread
From: Stefano Babic @ 2011-09-16 9:46 UTC (permalink / raw)
To: u-boot
The flea3 board is a custom board used in automotive.
Network (FEC), NOR, NAND and SPI are supported.
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
board/flea3/Makefile | 49 ++++++++
board/flea3/flea3.c | 254 +++++++++++++++++++++++++++++++++++++++
board/flea3/lowlevel_init.S | 79 ++++++++++++
boards.cfg | 1 +
include/configs/flea3.h | 280 +++++++++++++++++++++++++++++++++++++++++++
5 files changed, 663 insertions(+), 0 deletions(-)
create mode 100644 board/flea3/Makefile
create mode 100644 board/flea3/flea3.c
create mode 100644 board/flea3/lowlevel_init.S
create mode 100644 include/configs/flea3.h
diff --git a/board/flea3/Makefile b/board/flea3/Makefile
new file mode 100644
index 0000000..f5ad494
--- /dev/null
+++ b/board/flea3/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := flea3.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/flea3/flea3.c b/board/flea3/flea3.c
new file mode 100644
index 0000000..90201e3
--- /dev/null
+++ b/board/flea3/flea3.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+#define ESDCTL_0x92220000 0x92220000
+#define ESDCTL_0xA2220000 0xA2220000
+#define ESDCTL_0xB2220000 0xB2220000
+#define ESDCTL_0x82228080 0x82228080
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_PRECHARGE 0x00000400
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+#define ESDCTL_DELAY_LINE5 0x00F49F00
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+void board_setup_sdram(void)
+{
+ u32 val;
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ /* Initialize MISC register for DDR2 */
+ val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+ ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+ writel(val, &esdc->esdmisc);
+ val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+ writel(val, &esdc->esdmisc);
+
+ /*
+ * according to DDR2 specs, wait a while before
+ * the PRECHARGE_ALL command
+ */
+ sdelay(0x20000);
+
+ /* Load DDR2 config and timing */
+ writel(ESDCTL_DDR2_CONFIG, &esdc->esdcfg1);
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR + ESDCTL_PRECHARGE);
+
+ /* Load mode */
+ writel(ESDCTL_0xB2220000,
+ &esdc->esdctl1);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EMR2); /* EMRS2 */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EMR3); /* EMRS3 */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR + ESDCTL_PRECHARGE);
+
+ /* Set mode auto refresh : at least two refresh are required */
+ writel(ESDCTL_0xA2220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR);
+ writel(0xda, CSD1_BASE_ADDR);
+
+ writel(ESDCTL_0xB2220000,
+ &esdc->esdctl1);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_MR);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_OCD_DEFAULT);
+
+ /* OCD mode exit */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+ /* Set normal mode */
+ writel(ESDCTL_0x82228080,
+ &esdc->esdctl1);
+
+ sdelay(0x20000);
+
+ /* Do not set delay lines, only for MDDR */
+}
+
+static void setup_iomux_uart3(void)
+{
+ mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
+ mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
+}
+
+static void setup_iomux_i2c(void)
+{
+ int pad;
+
+ mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+ pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+ | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+ mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+ mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+
+ mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
+ mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
+
+ mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
+ mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+ mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+}
+
+int board_early_init_f(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+ writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+ /* Set the core to run at 532 Mhz */
+ writel(0x00001000, &ccm->pdr0);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_uart3();
+ setup_iomux_i2c();
+ setup_iomux_fec();
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
diff --git a/board/flea3/lowlevel_init.S b/board/flea3/lowlevel_init.S
new file mode 100644
index 0000000..2f42fc9
--- /dev/null
+++ b/board/flea3/lowlevel_init.S
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * Configuration for the flea3 board.
+ * These defines are used by the included macros and must
+ * be defined first
+ */
+#define AIPS_MPR_CONFIG 0x77777777
+#define AIPS_OPACR_CONFIG 0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG 0x00302154
+
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG 0x00000010
+
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG 0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+#define M3IF_CONFIG 0x00000040
+
+#define CCM_PDR0_CONFIG 0x00801000
+
+/*
+ * includes MX35 utility macros
+ */
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ mov pc, lr
diff --git a/boards.cfg b/boards.cfg
index d5fc5cb..4fc2051 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -44,6 +44,7 @@ imx31_phycore_eet arm arm1136 imx31_phycore -
mx31pdk_nand arm arm1136 mx31pdk freescale mx31 mx31pdk:NAND_U_BOOT
mx31pdk arm arm1136 - freescale mx31 mx31pdk:SKIP_LOWLEVEL_INIT
mx35pdk arm arm1136 - freescale mx35
+flea3 arm arm1136 - - mx35
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
integratorap_cm720t arm arm720t integrator armltd - integratorap
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
new file mode 100644
index 0000000..747b108
--- /dev/null
+++ b/include/configs/flea3.h
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the flea3 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* This is required to setup the ESDC controller */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX35_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "flea3 U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD1_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE CSD1_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:196m(root1),196m(root2),-(user);" \
+ "physmap-flash.0:512k(u-boot),64k(env1)," \
+ "64k(env2),3776k(kernel1),3776k(kernel2)"
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME flea3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=90800000\0" \
+ "kernel_addr_r=90800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=if run net_self_load;then " \
+ "run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
+ "else echo Images not loades;fi\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +40000;" \
+ "erase ${uboot_addr} +40000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH 8/8] MX35: add support for flea3 board
2011-09-16 9:46 ` [U-Boot] [PATCH 8/8] MX35: add support for flea3 board Stefano Babic
@ 2011-09-16 11:48 ` Fabio Estevam
2011-09-16 11:56 ` Stefano Babic
2011-09-16 11:49 ` Fabio Estevam
` (2 subsequent siblings)
3 siblings, 1 reply; 29+ messages in thread
From: Fabio Estevam @ 2011-09-16 11:48 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Fri, Sep 16, 2011 at 6:46 AM, Stefano Babic <sbabic@denx.de> wrote:
..
> +void board_setup_sdram(void)
> +{
> + ? ? ? u32 val;
> + ? ? ? struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
> +
> + ? ? ? /* Initialize with default values both CSD0/1 */
> + ? ? ? writel(0x2000, &esdc->esdctl0);
> + ? ? ? writel(0x2000, &esdc->esdctl1);
On other boards we setup the SDRAM in lowlevel_init.S and here you do
it on the board file.
Shouldn?t this be setup in lowlevel_init.S for consistency?
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 29+ messages in thread* [U-Boot] [PATCH 8/8] MX35: add support for flea3 board
2011-09-16 11:48 ` Fabio Estevam
@ 2011-09-16 11:56 ` Stefano Babic
0 siblings, 0 replies; 29+ messages in thread
From: Stefano Babic @ 2011-09-16 11:56 UTC (permalink / raw)
To: u-boot
On 09/16/2011 01:48 PM, Fabio Estevam wrote:
> Hi Stefano,
>
Hi Fabio,
> On Fri, Sep 16, 2011 at 6:46 AM, Stefano Babic <sbabic@denx.de> wrote:
> ..
>> +void board_setup_sdram(void)
>> +{
>> + u32 val;
>> + struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
>> +
>> + /* Initialize with default values both CSD0/1 */
>> + writel(0x2000, &esdc->esdctl0);
>> + writel(0x2000, &esdc->esdctl1);
>
> On other boards we setup the SDRAM in lowlevel_init.S and here you do
> it on the board file.
>
> Shouldn?t this be setup in lowlevel_init.S for consistency?
Really the idea is to get rid (as much as possible) of lowlevel_init.S
and make the whole setup in C code.
This board can be then the first one (MX3) doing that, that makes the
code much more readable - and I see in recent patches that this is
pushed for other architectures, too (I mean Heiko's patches for davinci
AM1808). And this is done since a lot of time for some PowerPC boards.
The question arises if the other boards (at least the mx35pdk..) should
be updated in the same way...
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 29+ messages in thread
* [U-Boot] [PATCH 8/8] MX35: add support for flea3 board
2011-09-16 9:46 ` [U-Boot] [PATCH 8/8] MX35: add support for flea3 board Stefano Babic
2011-09-16 11:48 ` Fabio Estevam
@ 2011-09-16 11:49 ` Fabio Estevam
2011-09-16 11:50 ` Stefano Babic
2011-09-20 11:53 ` [U-Boot] [PATCH V2 " Stefano Babic
2011-10-06 21:29 ` [U-Boot] [PATCH " Wolfgang Denk
3 siblings, 1 reply; 29+ messages in thread
From: Fabio Estevam @ 2011-09-16 11:49 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On Fri, Sep 16, 2011 at 6:46 AM, Stefano Babic <sbabic@denx.de> wrote:
> The flea3 board is a custom board used in automotive.
> Network (FEC), NOR, NAND and SPI are supported.
>
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> ---
> ?board/flea3/Makefile ? ? ? ?| ? 49 ++++++++
> ?board/flea3/flea3.c ? ? ? ? | ?254 +++++++++++++++++++++++++++++++++++++++
> ?board/flea3/lowlevel_init.S | ? 79 ++++++++++++
> ?boards.cfg ? ? ? ? ? ? ? ? ?| ? ?1 +
> ?include/configs/flea3.h ? ? | ?280 +++++++++++++++++++++++++++++++++++++++++++
> ?5 files changed, 663 insertions(+), 0 deletions(-)
> ?create mode 100644 board/flea3/Makefile
> ?create mode 100644 board/flea3/flea3.c
> ?create mode 100644 board/flea3/lowlevel_init.S
> ?create mode 100644 include/configs/flea3.h
You missed an entry in MAINTAINERS file.
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 29+ messages in thread
* [U-Boot] [PATCH 8/8] MX35: add support for flea3 board
2011-09-16 11:49 ` Fabio Estevam
@ 2011-09-16 11:50 ` Stefano Babic
0 siblings, 0 replies; 29+ messages in thread
From: Stefano Babic @ 2011-09-16 11:50 UTC (permalink / raw)
To: u-boot
On 09/16/2011 01:49 PM, Fabio Estevam wrote:
> Hi Stefano,
>
> On Fri, Sep 16, 2011 at 6:46 AM, Stefano Babic <sbabic@denx.de> wrote:
>> The flea3 board is a custom board used in automotive.
>> Network (FEC), NOR, NAND and SPI are supported.
>>
>> Signed-off-by: Stefano Babic <sbabic@denx.de>
>> ---
>> board/flea3/Makefile | 49 ++++++++
>> board/flea3/flea3.c | 254 +++++++++++++++++++++++++++++++++++++++
>> board/flea3/lowlevel_init.S | 79 ++++++++++++
>> boards.cfg | 1 +
>> include/configs/flea3.h | 280 +++++++++++++++++++++++++++++++++++++++++++
>> 5 files changed, 663 insertions(+), 0 deletions(-)
>> create mode 100644 board/flea3/Makefile
>> create mode 100644 board/flea3/flea3.c
>> create mode 100644 board/flea3/lowlevel_init.S
>> create mode 100644 include/configs/flea3.h
>
> You missed an entry in MAINTAINERS file.
Ok, thanks - fixed in V2.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 29+ messages in thread
* [U-Boot] [PATCH V2 8/8] MX35: add support for flea3 board
2011-09-16 9:46 ` [U-Boot] [PATCH 8/8] MX35: add support for flea3 board Stefano Babic
2011-09-16 11:48 ` Fabio Estevam
2011-09-16 11:49 ` Fabio Estevam
@ 2011-09-20 11:53 ` Stefano Babic
2011-10-06 21:29 ` [U-Boot] [PATCH " Wolfgang Denk
3 siblings, 0 replies; 29+ messages in thread
From: Stefano Babic @ 2011-09-20 11:53 UTC (permalink / raw)
To: u-boot
The flea3 board is a custom board used in automotive.
Network (FEC), NOR, NAND and SPI are supported.
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
Changes since V1:
- add missing entry in MAINTAINERS (F. Estevam)
MAINTAINERS | 1 +
board/flea3/Makefile | 49 ++++++++
board/flea3/flea3.c | 254 +++++++++++++++++++++++++++++++++++++++
board/flea3/lowlevel_init.S | 79 ++++++++++++
boards.cfg | 1 +
include/configs/flea3.h | 280 +++++++++++++++++++++++++++++++++++++++++++
6 files changed, 664 insertions(+), 0 deletions(-)
create mode 100644 board/flea3/Makefile
create mode 100644 board/flea3/flea3.c
create mode 100644 board/flea3/lowlevel_init.S
create mode 100644 include/configs/flea3.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2f60a60..af7de17 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -565,6 +565,7 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
Stefano Babic <sbabic@denx.de>
ea20 davinci
+ flea3 i.MX35
mx35pdk i.MX35
mx51evk i.MX51
polaris xscale/pxa
diff --git a/board/flea3/Makefile b/board/flea3/Makefile
new file mode 100644
index 0000000..f5ad494
--- /dev/null
+++ b/board/flea3/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := flea3.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/flea3/flea3.c b/board/flea3/flea3.c
new file mode 100644
index 0000000..90201e3
--- /dev/null
+++ b/board/flea3/flea3.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+#define ESDCTL_0x92220000 0x92220000
+#define ESDCTL_0xA2220000 0xA2220000
+#define ESDCTL_0xB2220000 0xB2220000
+#define ESDCTL_0x82228080 0x82228080
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_PRECHARGE 0x00000400
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+#define ESDCTL_DELAY_LINE5 0x00F49F00
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+void board_setup_sdram(void)
+{
+ u32 val;
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ /* Initialize MISC register for DDR2 */
+ val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+ ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+ writel(val, &esdc->esdmisc);
+ val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+ writel(val, &esdc->esdmisc);
+
+ /*
+ * according to DDR2 specs, wait a while before
+ * the PRECHARGE_ALL command
+ */
+ sdelay(0x20000);
+
+ /* Load DDR2 config and timing */
+ writel(ESDCTL_DDR2_CONFIG, &esdc->esdcfg1);
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR + ESDCTL_PRECHARGE);
+
+ /* Load mode */
+ writel(ESDCTL_0xB2220000,
+ &esdc->esdctl1);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EMR2); /* EMRS2 */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EMR3); /* EMRS3 */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR + ESDCTL_PRECHARGE);
+
+ /* Set mode auto refresh : at least two refresh are required */
+ writel(ESDCTL_0xA2220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR);
+ writel(0xda, CSD1_BASE_ADDR);
+
+ writel(ESDCTL_0xB2220000,
+ &esdc->esdctl1);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_MR);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_OCD_DEFAULT);
+
+ /* OCD mode exit */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+ /* Set normal mode */
+ writel(ESDCTL_0x82228080,
+ &esdc->esdctl1);
+
+ sdelay(0x20000);
+
+ /* Do not set delay lines, only for MDDR */
+}
+
+static void setup_iomux_uart3(void)
+{
+ mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
+ mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
+}
+
+static void setup_iomux_i2c(void)
+{
+ int pad;
+
+ mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+ pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+ | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+ mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+ mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+
+ mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
+ mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
+
+ mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
+ mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+ mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+}
+
+int board_early_init_f(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+ writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+ /* Set the core to run at 532 Mhz */
+ writel(0x00001000, &ccm->pdr0);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_uart3();
+ setup_iomux_i2c();
+ setup_iomux_fec();
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
diff --git a/board/flea3/lowlevel_init.S b/board/flea3/lowlevel_init.S
new file mode 100644
index 0000000..2f42fc9
--- /dev/null
+++ b/board/flea3/lowlevel_init.S
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * Configuration for the flea3 board.
+ * These defines are used by the included macros and must
+ * be defined first
+ */
+#define AIPS_MPR_CONFIG 0x77777777
+#define AIPS_OPACR_CONFIG 0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG 0x00302154
+
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG 0x00000010
+
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG 0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+#define M3IF_CONFIG 0x00000040
+
+#define CCM_PDR0_CONFIG 0x00801000
+
+/*
+ * includes MX35 utility macros
+ */
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ mov pc, lr
diff --git a/boards.cfg b/boards.cfg
index d5fc5cb..4fc2051 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -44,6 +44,7 @@ imx31_phycore_eet arm arm1136 imx31_phycore -
mx31pdk_nand arm arm1136 mx31pdk freescale mx31 mx31pdk:NAND_U_BOOT
mx31pdk arm arm1136 - freescale mx31 mx31pdk:SKIP_LOWLEVEL_INIT
mx35pdk arm arm1136 - freescale mx35
+flea3 arm arm1136 - - mx35
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
integratorap_cm720t arm arm720t integrator armltd - integratorap
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
new file mode 100644
index 0000000..747b108
--- /dev/null
+++ b/include/configs/flea3.h
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the flea3 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* This is required to setup the ESDC controller */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX35_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "flea3 U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD1_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE CSD1_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:196m(root1),196m(root2),-(user);" \
+ "physmap-flash.0:512k(u-boot),64k(env1)," \
+ "64k(env2),3776k(kernel1),3776k(kernel2)"
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME flea3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=90800000\0" \
+ "kernel_addr_r=90800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=if run net_self_load;then " \
+ "run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
+ "else echo Images not loades;fi\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +40000;" \
+ "erase ${uboot_addr} +40000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH 8/8] MX35: add support for flea3 board
2011-09-16 9:46 ` [U-Boot] [PATCH 8/8] MX35: add support for flea3 board Stefano Babic
` (2 preceding siblings ...)
2011-09-20 11:53 ` [U-Boot] [PATCH V2 " Stefano Babic
@ 2011-10-06 21:29 ` Wolfgang Denk
3 siblings, 0 replies; 29+ messages in thread
From: Wolfgang Denk @ 2011-10-06 21:29 UTC (permalink / raw)
To: u-boot
Dear Stefano Babic,
In message <1316166383-11314-8-git-send-email-sbabic@denx.de> you wrote:
> The flea3 board is a custom board used in automotive.
> Network (FEC), NOR, NAND and SPI are supported.
>
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> ---
> board/flea3/Makefile | 49 ++++++++
> board/flea3/flea3.c | 254 +++++++++++++++++++++++++++++++++++++++
> board/flea3/lowlevel_init.S | 79 ++++++++++++
> boards.cfg | 1 +
> include/configs/flea3.h | 280 +++++++++++++++++++++++++++++++++++++++++++
> 5 files changed, 663 insertions(+), 0 deletions(-)
> create mode 100644 board/flea3/Makefile
> create mode 100644 board/flea3/flea3.c
> create mode 100644 board/flea3/lowlevel_init.S
> create mode 100644 include/configs/flea3.h
Checkpatch says:
total: 0 errors, 1 warnings, 669 lines checked
Please clean up and resubmit. Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
No one can guarantee the actions of another.
-- Spock, "Day of the Dove", stardate unknown
^ permalink raw reply [flat|nested] 29+ messages in thread
* [U-Boot] [PATCH V3 8/8] MX35: add support for flea3 board
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
` (6 preceding siblings ...)
2011-09-16 9:46 ` [U-Boot] [PATCH 8/8] MX35: add support for flea3 board Stefano Babic
@ 2011-09-20 14:12 ` Stefano Babic
2011-10-06 21:28 ` Wolfgang Denk
2011-10-06 22:38 ` [U-Boot] [PATCH V4 " Stefano Babic
` (3 subsequent siblings)
11 siblings, 1 reply; 29+ messages in thread
From: Stefano Babic @ 2011-09-20 14:12 UTC (permalink / raw)
To: u-boot
The flea3 board is a custom board by CarMediaLab used
in automotive.
Network (FEC), NOR, NAND and SPI are supported.
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
Changes since V2:
- put the board into manufacturer's directory (CarMediaLab)
Changes since V1:
- add missing entry in MAINTAINERS (F. Estevam)
MAINTAINERS | 1 +
board/CarMediaLab/flea3/Makefile | 49 ++++++
board/CarMediaLab/flea3/flea3.c | 254 ++++++++++++++++++++++++++++
board/CarMediaLab/flea3/lowlevel_init.S | 79 +++++++++
boards.cfg | 1 +
include/configs/flea3.h | 280 +++++++++++++++++++++++++++++++
6 files changed, 664 insertions(+), 0 deletions(-)
create mode 100644 board/CarMediaLab/flea3/Makefile
create mode 100644 board/CarMediaLab/flea3/flea3.c
create mode 100644 board/CarMediaLab/flea3/lowlevel_init.S
create mode 100644 include/configs/flea3.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2f60a60..af7de17 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -565,6 +565,7 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
Stefano Babic <sbabic@denx.de>
ea20 davinci
+ flea3 i.MX35
mx35pdk i.MX35
mx51evk i.MX51
polaris xscale/pxa
diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile
new file mode 100644
index 0000000..f5ad494
--- /dev/null
+++ b/board/CarMediaLab/flea3/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := flea3.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
new file mode 100644
index 0000000..90201e3
--- /dev/null
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+#define ESDCTL_0x92220000 0x92220000
+#define ESDCTL_0xA2220000 0xA2220000
+#define ESDCTL_0xB2220000 0xB2220000
+#define ESDCTL_0x82228080 0x82228080
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_PRECHARGE 0x00000400
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+#define ESDCTL_DELAY_LINE5 0x00F49F00
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+void board_setup_sdram(void)
+{
+ u32 val;
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ /* Initialize MISC register for DDR2 */
+ val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+ ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+ writel(val, &esdc->esdmisc);
+ val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+ writel(val, &esdc->esdmisc);
+
+ /*
+ * according to DDR2 specs, wait a while before
+ * the PRECHARGE_ALL command
+ */
+ sdelay(0x20000);
+
+ /* Load DDR2 config and timing */
+ writel(ESDCTL_DDR2_CONFIG, &esdc->esdcfg1);
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR + ESDCTL_PRECHARGE);
+
+ /* Load mode */
+ writel(ESDCTL_0xB2220000,
+ &esdc->esdctl1);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EMR2); /* EMRS2 */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EMR3); /* EMRS3 */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR + ESDCTL_PRECHARGE);
+
+ /* Set mode auto refresh : at least two refresh are required */
+ writel(ESDCTL_0xA2220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR);
+ writel(0xda, CSD1_BASE_ADDR);
+
+ writel(ESDCTL_0xB2220000,
+ &esdc->esdctl1);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_MR);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_OCD_DEFAULT);
+
+ /* OCD mode exit */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+ /* Set normal mode */
+ writel(ESDCTL_0x82228080,
+ &esdc->esdctl1);
+
+ sdelay(0x20000);
+
+ /* Do not set delay lines, only for MDDR */
+}
+
+static void setup_iomux_uart3(void)
+{
+ mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
+ mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
+}
+
+static void setup_iomux_i2c(void)
+{
+ int pad;
+
+ mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+ pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+ | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+ mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+ mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+
+ mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
+ mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
+
+ mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
+ mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+ mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+}
+
+int board_early_init_f(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+ writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+ /* Set the core to run at 532 Mhz */
+ writel(0x00001000, &ccm->pdr0);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_uart3();
+ setup_iomux_i2c();
+ setup_iomux_fec();
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S
new file mode 100644
index 0000000..2f42fc9
--- /dev/null
+++ b/board/CarMediaLab/flea3/lowlevel_init.S
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * Configuration for the flea3 board.
+ * These defines are used by the included macros and must
+ * be defined first
+ */
+#define AIPS_MPR_CONFIG 0x77777777
+#define AIPS_OPACR_CONFIG 0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG 0x00302154
+
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG 0x00000010
+
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG 0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+#define M3IF_CONFIG 0x00000040
+
+#define CCM_PDR0_CONFIG 0x00801000
+
+/*
+ * includes MX35 utility macros
+ */
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ mov pc, lr
diff --git a/boards.cfg b/boards.cfg
index d5fc5cb..853a5e4 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -43,6 +43,7 @@ imx31_phycore arm arm1136 - -
imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET
mx31pdk_nand arm arm1136 mx31pdk freescale mx31 mx31pdk:NAND_U_BOOT
mx31pdk arm arm1136 - freescale mx31 mx31pdk:SKIP_LOWLEVEL_INIT
+flea3 arm arm1136 - CarMediaLab mx35
mx35pdk arm arm1136 - freescale mx35
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
new file mode 100644
index 0000000..747b108
--- /dev/null
+++ b/include/configs/flea3.h
@@ -0,0 +1,280 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the flea3 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* This is required to setup the ESDC controller */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX35_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "flea3 U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD1_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE CSD1_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:196m(root1),196m(root2),-(user);" \
+ "physmap-flash.0:512k(u-boot),64k(env1)," \
+ "64k(env2),3776k(kernel1),3776k(kernel2)"
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME flea3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=90800000\0" \
+ "kernel_addr_r=90800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=if run net_self_load;then " \
+ "run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
+ "else echo Images not loades;fi\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +40000;" \
+ "erase ${uboot_addr} +40000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH V3 8/8] MX35: add support for flea3 board
2011-09-20 14:12 ` [U-Boot] [PATCH V3 " Stefano Babic
@ 2011-10-06 21:28 ` Wolfgang Denk
2011-10-06 22:03 ` stefano babic
0 siblings, 1 reply; 29+ messages in thread
From: Wolfgang Denk @ 2011-10-06 21:28 UTC (permalink / raw)
To: u-boot
Dear Stefano Babic,
In message <1316527939-7212-1-git-send-email-sbabic@denx.de> you wrote:
> The flea3 board is a custom board by CarMediaLab used
> in automotive.
> Network (FEC), NOR, NAND and SPI are supported.
>
> Signed-off-by: Stefano Babic <sbabic@denx.de>
> ---
>
> Changes since V2:
> - put the board into manufacturer's directory (CarMediaLab)
>
> Changes since V1:
> - add missing entry in MAINTAINERS (F. Estevam)
>
> MAINTAINERS | 1 +
> board/CarMediaLab/flea3/Makefile | 49 ++++++
> board/CarMediaLab/flea3/flea3.c | 254 ++++++++++++++++++++++++++++
> board/CarMediaLab/flea3/lowlevel_init.S | 79 +++++++++
> boards.cfg | 1 +
> include/configs/flea3.h | 280 +++++++++++++++++++++++++++++++
> 6 files changed, 664 insertions(+), 0 deletions(-)
> create mode 100644 board/CarMediaLab/flea3/Makefile
> create mode 100644 board/CarMediaLab/flea3/flea3.c
> create mode 100644 board/CarMediaLab/flea3/lowlevel_init.S
> create mode 100644 include/configs/flea3.h
Checkpatch says:
total: 0 errors, 1 warnings, 676 lines checked
Please clean up and resubmit. Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Hegel was right when he said that we learn from history that man can
never learn anything from history. - George Bernard Shaw
^ permalink raw reply [flat|nested] 29+ messages in thread
* [U-Boot] [PATCH V3 8/8] MX35: add support for flea3 board
2011-10-06 21:28 ` Wolfgang Denk
@ 2011-10-06 22:03 ` stefano babic
0 siblings, 0 replies; 29+ messages in thread
From: stefano babic @ 2011-10-06 22:03 UTC (permalink / raw)
To: u-boot
Am 06/10/2011 23:28, schrieb Wolfgang Denk:
> Dear Stefano Babic,
>
> In message <1316527939-7212-1-git-send-email-sbabic@denx.de> you wrote:
>> The flea3 board is a custom board by CarMediaLab used
>> in automotive.
>> Network (FEC), NOR, NAND and SPI are supported.
>>
>> Signed-off-by: Stefano Babic <sbabic@denx.de>
>> ---
>>
>> Changes since V2:
>> - put the board into manufacturer's directory (CarMediaLab)
>>
>> Changes since V1:
>> - add missing entry in MAINTAINERS (F. Estevam)
>>
>> MAINTAINERS | 1 +
>> board/CarMediaLab/flea3/Makefile | 49 ++++++
>> board/CarMediaLab/flea3/flea3.c | 254 ++++++++++++++++++++++++++++
>> board/CarMediaLab/flea3/lowlevel_init.S | 79 +++++++++
>> boards.cfg | 1 +
>> include/configs/flea3.h | 280 +++++++++++++++++++++++++++++++
>> 6 files changed, 664 insertions(+), 0 deletions(-)
>> create mode 100644 board/CarMediaLab/flea3/Makefile
>> create mode 100644 board/CarMediaLab/flea3/flea3.c
>> create mode 100644 board/CarMediaLab/flea3/lowlevel_init.S
>> create mode 100644 include/configs/flea3.h
>
> Checkpatch says:
>
> total: 0 errors, 1 warnings, 676 lines checked
>
Thanks, it seems I forget to rerun checkpatch again - I fix it.
Best regards,
Stefanio Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 29+ messages in thread
* [U-Boot] [PATCH V4 8/8] MX35: add support for flea3 board
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
` (7 preceding siblings ...)
2011-09-20 14:12 ` [U-Boot] [PATCH V3 " Stefano Babic
@ 2011-10-06 22:38 ` Stefano Babic
[not found] ` <CAOMZO5DqqOiUfeCTKFQTy33_fTsUHAMhSQ59bU0PnuU1AZ8Ckg@mail.gmail.com>
2011-10-08 12:33 ` [U-Boot] [PATCH V5 " Stefano Babic
` (2 subsequent siblings)
11 siblings, 1 reply; 29+ messages in thread
From: Stefano Babic @ 2011-10-06 22:38 UTC (permalink / raw)
To: u-boot
The flea3 board is a custom board by CarMediaLab used
in automotive.
Network (FEC), NOR, NAND and SPI are supported.
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
Changes since V3:
- fix checkpatch warnings (Wolfgang Denk)
Changes since V2:
- put the board into manufacturer's directory (CarMediaLab)
Changes since V1:
- add missing entry in MAINTAINERS (F. Estevam)
MAINTAINERS | 1 +
board/CarMediaLab/flea3/Makefile | 49 ++++++
board/CarMediaLab/flea3/flea3.c | 254 ++++++++++++++++++++++++++++
board/CarMediaLab/flea3/lowlevel_init.S | 79 +++++++++
boards.cfg | 5 +
include/configs/flea3.h | 281 +++++++++++++++++++++++++++++++
6 files changed, 669 insertions(+), 0 deletions(-)
create mode 100644 board/CarMediaLab/flea3/Makefile
create mode 100644 board/CarMediaLab/flea3/flea3.c
create mode 100644 board/CarMediaLab/flea3/lowlevel_init.S
create mode 100644 include/configs/flea3.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c10996c..24adb03 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -565,6 +565,7 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
Stefano Babic <sbabic@denx.de>
ea20 davinci
+ flea3 i.MX35
mx35pdk i.MX35
mx51evk i.MX51
polaris xscale/pxa
diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile
new file mode 100644
index 0000000..f5ad494
--- /dev/null
+++ b/board/CarMediaLab/flea3/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := flea3.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
new file mode 100644
index 0000000..90201e3
--- /dev/null
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+#define ESDCTL_0x92220000 0x92220000
+#define ESDCTL_0xA2220000 0xA2220000
+#define ESDCTL_0xB2220000 0xB2220000
+#define ESDCTL_0x82228080 0x82228080
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_PRECHARGE 0x00000400
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+#define ESDCTL_DELAY_LINE5 0x00F49F00
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+void board_setup_sdram(void)
+{
+ u32 val;
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ /* Initialize MISC register for DDR2 */
+ val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+ ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+ writel(val, &esdc->esdmisc);
+ val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+ writel(val, &esdc->esdmisc);
+
+ /*
+ * according to DDR2 specs, wait a while before
+ * the PRECHARGE_ALL command
+ */
+ sdelay(0x20000);
+
+ /* Load DDR2 config and timing */
+ writel(ESDCTL_DDR2_CONFIG, &esdc->esdcfg1);
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR + ESDCTL_PRECHARGE);
+
+ /* Load mode */
+ writel(ESDCTL_0xB2220000,
+ &esdc->esdctl1);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EMR2); /* EMRS2 */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EMR3); /* EMRS3 */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR + ESDCTL_PRECHARGE);
+
+ /* Set mode auto refresh : at least two refresh are required */
+ writel(ESDCTL_0xA2220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR);
+ writel(0xda, CSD1_BASE_ADDR);
+
+ writel(ESDCTL_0xB2220000,
+ &esdc->esdctl1);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_MR);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_OCD_DEFAULT);
+
+ /* OCD mode exit */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+ /* Set normal mode */
+ writel(ESDCTL_0x82228080,
+ &esdc->esdctl1);
+
+ sdelay(0x20000);
+
+ /* Do not set delay lines, only for MDDR */
+}
+
+static void setup_iomux_uart3(void)
+{
+ mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
+ mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
+}
+
+static void setup_iomux_i2c(void)
+{
+ int pad;
+
+ mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+ pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+ | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+ mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+ mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+
+ mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
+ mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
+
+ mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
+ mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+ mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+}
+
+int board_early_init_f(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+ writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+ /* Set the core to run at 532 Mhz */
+ writel(0x00001000, &ccm->pdr0);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_uart3();
+ setup_iomux_i2c();
+ setup_iomux_fec();
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S
new file mode 100644
index 0000000..2f42fc9
--- /dev/null
+++ b/board/CarMediaLab/flea3/lowlevel_init.S
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * Configuration for the flea3 board.
+ * These defines are used by the included macros and must
+ * be defined first
+ */
+#define AIPS_MPR_CONFIG 0x77777777
+#define AIPS_OPACR_CONFIG 0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG 0x00302154
+
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG 0x00000010
+
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG 0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+#define M3IF_CONFIG 0x00000040
+
+#define CCM_PDR0_CONFIG 0x00801000
+
+/*
+ * includes MX35 utility macros
+ */
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ mov pc, lr
diff --git a/boards.cfg b/boards.cfg
index c485cd7..a8e9431 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -39,6 +39,11 @@ integratorcp_cm1136 arm arm1136 integrator armltd
qong arm arm1136 - davedenx mx31
mx31ads arm arm1136 - freescale mx31
imx31_litekit arm arm1136 - logicpd mx31
+imx31_phycore arm arm1136 - - mx31
+imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET
+mx31pdk_nand arm arm1136 mx31pdk freescale mx31 mx31pdk:NAND_U_BOOT
+mx31pdk arm arm1136 - freescale mx31 mx31pdk:SKIP_LOWLEVEL_INIT
+flea3 arm arm1136 - CarMediaLab mx35
mx35pdk arm arm1136 - freescale mx35
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
new file mode 100644
index 0000000..eb351f1
--- /dev/null
+++ b/include/configs/flea3.h
@@ -0,0 +1,281 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the flea3 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* This is required to setup the ESDC controller */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX35_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "flea3 U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD1_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE CSD1_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:196m(root1)," \
+ "196m(root2),-(user);" \
+ "physmap-flash.0:512k(u-boot),64k(env1)," \
+ "64k(env2),3776k(kernel1),3776k(kernel2)"
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME flea3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=90800000\0" \
+ "kernel_addr_r=90800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=if run net_self_load;then " \
+ "run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
+ "else echo Images not loades;fi\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +40000;" \
+ "erase ${uboot_addr} +40000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH V5 8/8] MX35: add support for flea3 board
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
` (8 preceding siblings ...)
2011-10-06 22:38 ` [U-Boot] [PATCH V4 " Stefano Babic
@ 2011-10-08 12:33 ` Stefano Babic
2011-10-15 8:06 ` [U-Boot] [PATCH V2 5/8] ARM: moved general function to arm/lib Stefano Babic
2011-10-24 9:58 ` [U-Boot] [PATCH V6] MX35: add support for flea3 board Stefano Babic
11 siblings, 0 replies; 29+ messages in thread
From: Stefano Babic @ 2011-10-08 12:33 UTC (permalink / raw)
To: u-boot
The flea3 board is a custom board by CarMediaLab used
in automotive.
Network (FEC), NOR, NAND and SPI are supported.
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
Changes since V4:
- boards.cfg maust have a new entry only for flea3 (Fabio Estevam)
Changes since V3:
- fix checkpatch warnings (Wolfgang Denk)
Changes since V2:
- put the board into manufacturer's directory (CarMediaLab)
Changes since V1:
- add missing entry in MAINTAINERS (F. Estevam)
MAINTAINERS | 1 +
board/CarMediaLab/flea3/Makefile | 49 ++++++
board/CarMediaLab/flea3/flea3.c | 254 ++++++++++++++++++++++++++++
board/CarMediaLab/flea3/lowlevel_init.S | 79 +++++++++
boards.cfg | 1 +
include/configs/flea3.h | 281 +++++++++++++++++++++++++++++++
6 files changed, 665 insertions(+), 0 deletions(-)
create mode 100644 board/CarMediaLab/flea3/Makefile
create mode 100644 board/CarMediaLab/flea3/flea3.c
create mode 100644 board/CarMediaLab/flea3/lowlevel_init.S
create mode 100644 include/configs/flea3.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c10996c..24adb03 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -565,6 +565,7 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
Stefano Babic <sbabic@denx.de>
ea20 davinci
+ flea3 i.MX35
mx35pdk i.MX35
mx51evk i.MX51
polaris xscale/pxa
diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile
new file mode 100644
index 0000000..f5ad494
--- /dev/null
+++ b/board/CarMediaLab/flea3/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := flea3.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
new file mode 100644
index 0000000..90201e3
--- /dev/null
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+#define ESDCTL_0x92220000 0x92220000
+#define ESDCTL_0xA2220000 0xA2220000
+#define ESDCTL_0xB2220000 0xB2220000
+#define ESDCTL_0x82228080 0x82228080
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_PRECHARGE 0x00000400
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+#define ESDCTL_DELAY_LINE5 0x00F49F00
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+void board_setup_sdram(void)
+{
+ u32 val;
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ /* Initialize MISC register for DDR2 */
+ val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+ ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+ writel(val, &esdc->esdmisc);
+ val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+ writel(val, &esdc->esdmisc);
+
+ /*
+ * according to DDR2 specs, wait a while before
+ * the PRECHARGE_ALL command
+ */
+ sdelay(0x20000);
+
+ /* Load DDR2 config and timing */
+ writel(ESDCTL_DDR2_CONFIG, &esdc->esdcfg1);
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR + ESDCTL_PRECHARGE);
+
+ /* Load mode */
+ writel(ESDCTL_0xB2220000,
+ &esdc->esdctl1);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EMR2); /* EMRS2 */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EMR3); /* EMRS3 */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR + ESDCTL_PRECHARGE);
+
+ /* Set mode auto refresh : at least two refresh are required */
+ writel(ESDCTL_0xA2220000,
+ &esdc->esdctl1);
+ writel(0xda, CSD1_BASE_ADDR);
+ writel(0xda, CSD1_BASE_ADDR);
+
+ writel(ESDCTL_0xB2220000,
+ &esdc->esdctl1);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_MR);
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_OCD_DEFAULT);
+
+ /* OCD mode exit */
+ writeb(0xda, CSD1_BASE_ADDR + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+ /* Set normal mode */
+ writel(ESDCTL_0x82228080,
+ &esdc->esdctl1);
+
+ sdelay(0x20000);
+
+ /* Do not set delay lines, only for MDDR */
+}
+
+static void setup_iomux_uart3(void)
+{
+ mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
+ mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
+}
+
+static void setup_iomux_i2c(void)
+{
+ int pad;
+
+ mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+ pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+ | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+ mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+ mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+
+ mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
+ mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
+
+ mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
+ mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+ mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+}
+
+int board_early_init_f(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+ writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+ /* Set the core to run at 532 Mhz */
+ writel(0x00001000, &ccm->pdr0);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_uart3();
+ setup_iomux_i2c();
+ setup_iomux_fec();
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S
new file mode 100644
index 0000000..2f42fc9
--- /dev/null
+++ b/board/CarMediaLab/flea3/lowlevel_init.S
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * Configuration for the flea3 board.
+ * These defines are used by the included macros and must
+ * be defined first
+ */
+#define AIPS_MPR_CONFIG 0x77777777
+#define AIPS_OPACR_CONFIG 0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG 0x00302154
+
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG 0x00000010
+
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG 0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+#define M3IF_CONFIG 0x00000040
+
+#define CCM_PDR0_CONFIG 0x00801000
+
+/*
+ * includes MX35 utility macros
+ */
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ mov pc, lr
diff --git a/boards.cfg b/boards.cfg
index c485cd7..c466cf9 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -39,6 +39,7 @@ integratorcp_cm1136 arm arm1136 integrator armltd
qong arm arm1136 - davedenx mx31
mx31ads arm arm1136 - freescale mx31
imx31_litekit arm arm1136 - logicpd mx31
+flea3 arm arm1136 - CarMediaLab mx35
mx35pdk arm arm1136 - freescale mx35
omap2420h4 arm arm1136 - ti omap24xx
tnetv107x_evm arm arm1176 tnetv107xevm ti tnetv107x
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
new file mode 100644
index 0000000..eb351f1
--- /dev/null
+++ b/include/configs/flea3.h
@@ -0,0 +1,281 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the flea3 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* This is required to setup the ESDC controller */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX35_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "flea3 U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD1_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE CSD1_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:196m(root1)," \
+ "196m(root2),-(user);" \
+ "physmap-flash.0:512k(u-boot),64k(env1)," \
+ "64k(env2),3776k(kernel1),3776k(kernel2)"
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME flea3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=90800000\0" \
+ "kernel_addr_r=90800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=if run net_self_load;then " \
+ "run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
+ "else echo Images not loades;fi\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +40000;" \
+ "erase ${uboot_addr} +40000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH V2 5/8] ARM: moved general function to arm/lib
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
` (9 preceding siblings ...)
2011-10-08 12:33 ` [U-Boot] [PATCH V5 " Stefano Babic
@ 2011-10-15 8:06 ` Stefano Babic
2011-10-15 10:15 ` Albert ARIBAUD
2011-10-24 9:58 ` [U-Boot] [PATCH V6] MX35: add support for flea3 board Stefano Babic
11 siblings, 1 reply; 29+ messages in thread
From: Stefano Babic @ 2011-10-15 8:06 UTC (permalink / raw)
To: u-boot
Functions inside armv7/syslib can be used by other ARM
architectures, too. The file is added as part of
ARM library.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
CC: Wolfgang Denk <wd@denx.de>
---
Changes:
- use -C in git format-patch to detect renames
arch/arm/cpu/armv7/Makefile | 2 --
arch/arm/lib/Makefile | 2 ++
arch/arm/{cpu/armv7 => lib}/syslib.c | 0
3 files changed, 2 insertions(+), 2 deletions(-)
rename arch/arm/{cpu/armv7 => lib}/syslib.c (100%)
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 92a5a96..5b7f1c7 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,8 +32,6 @@ COBJS += cache_v7.o
COBJS += cpu.o
endif
-COBJS += syslib.o
-
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
START := $(addprefix $(obj),$(START))
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 300c8fa..c966aa7 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -48,6 +48,8 @@ SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
endif
+COBJS-y += syslib.o
+
SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
$(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/lib/syslib.c
similarity index 100%
rename from arch/arm/cpu/armv7/syslib.c
rename to arch/arm/lib/syslib.c
--
1.7.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [U-Boot] [PATCH V2 5/8] ARM: moved general function to arm/lib
2011-10-15 8:06 ` [U-Boot] [PATCH V2 5/8] ARM: moved general function to arm/lib Stefano Babic
@ 2011-10-15 10:15 ` Albert ARIBAUD
2011-10-15 11:12 ` Stefano Babic
0 siblings, 1 reply; 29+ messages in thread
From: Albert ARIBAUD @ 2011-10-15 10:15 UTC (permalink / raw)
To: u-boot
Hi Stefano,
Le 15/10/2011 10:06, Stefano Babic a ?crit :
> Functions inside armv7/syslib can be used by other ARM
> architectures, too. The file is added as part of
> ARM library.
>
> Signed-off-by: Stefano Babic<sbabic@denx.de>
> CC: Albert ARIBAUD<albert.u.boot@aribaud.net>
> CC: Wolfgang Denk<wd@denx.de>
> ---
>
> Changes:
>
> - use -C in git format-patch to detect renames
>
> arch/arm/cpu/armv7/Makefile | 2 --
> arch/arm/lib/Makefile | 2 ++
> arch/arm/{cpu/armv7 => lib}/syslib.c | 0
> 3 files changed, 2 insertions(+), 2 deletions(-)
> rename arch/arm/{cpu/armv7 => lib}/syslib.c (100%)
>
> diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
> index 92a5a96..5b7f1c7 100644
> --- a/arch/arm/cpu/armv7/Makefile
> +++ b/arch/arm/cpu/armv7/Makefile
> @@ -32,8 +32,6 @@ COBJS += cache_v7.o
> COBJS += cpu.o
> endif
>
> -COBJS += syslib.o
> -
> SRCS := $(START:.o=.S) $(COBJS:.o=.c)
> OBJS := $(addprefix $(obj),$(COBJS))
> START := $(addprefix $(obj),$(START))
> diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
> index 300c8fa..c966aa7 100644
> --- a/arch/arm/lib/Makefile
> +++ b/arch/arm/lib/Makefile
> @@ -48,6 +48,8 @@ SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o
> SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o
> endif
>
> +COBJS-y += syslib.o
> +
> SRCS := $(GLSOBJS:.o=.S) $(GLCOBJS:.o=.c) \
> $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
> OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
> diff --git a/arch/arm/cpu/armv7/syslib.c b/arch/arm/lib/syslib.c
> similarity index 100%
> rename from arch/arm/cpu/armv7/syslib.c
> rename to arch/arm/lib/syslib.c
I agree with Wofgang that sdelay() is redundant wrt udelay() and has
weaker semantics.
I'll add that sr32() is kind of not ARM specific, so I fail to see why
it should move to generic ARM, and besides, it is a half-baked solution
to the general problem of setting a bitfield in a register -- half-baked
in that it only applies to bits. Besides, There's been a long discussion
on this list about similar-minded helper macros, and the conclusion was
that keeping the operation explicitly as logical combinations of
bitmasks was the best way to let the reader know what is going on
without forcing them to look up a macro or function definition.
As for wait-on_value(), it is based on the same weak semantics as
sdelay(), i.e. a number of loops, the duration of which depends on many
factors and is thus undependable. Besides, if the field changes value
but is not the one expected, it wastes cycles waiting for the expected
one. This is inefficient especially of the field is of the form "one
value for "ok", many others for various failure cases", where even once
a failure is indicated, the code still loops waiting for an "ok" that
will never come.
I conclude like Wolfgang that despite this code having gone through
review unnoticed, it should not be promoted for wider use.
If some functionality of these three functions is desirable and cannot
be met with other means, please submit new code for general ARM
inclusion (and maybe consider adapting armv7 to this new code).
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 29+ messages in thread* [U-Boot] [PATCH V2 5/8] ARM: moved general function to arm/lib
2011-10-15 10:15 ` Albert ARIBAUD
@ 2011-10-15 11:12 ` Stefano Babic
0 siblings, 0 replies; 29+ messages in thread
From: Stefano Babic @ 2011-10-15 11:12 UTC (permalink / raw)
To: u-boot
On 10/15/2011 12:15 PM, Albert ARIBAUD wrote:
> Hi Stefano,
>
Hi Albert,
>
> I agree with Wofgang that sdelay() is redundant wrt udelay() and has
> weaker semantics.
>
> I'll add that sr32() is kind of not ARM specific, so I fail to see why
> it should move to generic ARM, and besides, it is a half-baked solution
> to the general problem of setting a bitfield in a register
Right, it is.
>
> I conclude like Wolfgang that despite this code having gone through
> review unnoticed, it should not be promoted for wider use.
Understood.
>
> If some functionality of these three functions is desirable and cannot
> be met with other means, please submit new code for general ARM
> inclusion (and maybe consider adapting armv7 to this new code).
I understand your points - and I agree with you, thanks for clarification.
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 29+ messages in thread
* [U-Boot] [PATCH V6] MX35: add support for flea3 board
2011-09-16 9:46 [U-Boot] [PATCH 1/8] MX35: added ESDC structure to imx-regs Stefano Babic
` (10 preceding siblings ...)
2011-10-15 8:06 ` [U-Boot] [PATCH V2 5/8] ARM: moved general function to arm/lib Stefano Babic
@ 2011-10-24 9:58 ` Stefano Babic
11 siblings, 0 replies; 29+ messages in thread
From: Stefano Babic @ 2011-10-24 9:58 UTC (permalink / raw)
To: u-boot
The flea3 board is a custom board by CarMediaLab used
in automotive.
Network (FEC), NOR, NAND and SPI are supported.
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
Changes since V5:
- drop sdelay after discussion on ML (W. Denk, A. Aribaud)
- modify dram initialization to work with both CSD0 and CSD1
- set GPIO3_1 to High due to hardware changes
Changes since V4:
- boards.cfg maust have a new entry only for flea3 (Fabio Estevam)
Changes since V3:
- fix checkpatch warnings (Wolfgang Denk)
Changes since V2:
- put the board into manufacturer's directory (CarMediaLab)
Changes since V1:
- add missing entry in MAINTAINERS (F. Estevam)
MAINTAINERS | 1 +
board/CarMediaLab/flea3/Makefile | 49 ++++++
board/CarMediaLab/flea3/flea3.c | 289 +++++++++++++++++++++++++++++++
board/CarMediaLab/flea3/lowlevel_init.S | 79 +++++++++
boards.cfg | 1 +
include/configs/flea3.h | 286 ++++++++++++++++++++++++++++++
6 files changed, 705 insertions(+), 0 deletions(-)
create mode 100644 board/CarMediaLab/flea3/Makefile
create mode 100644 board/CarMediaLab/flea3/flea3.c
create mode 100644 board/CarMediaLab/flea3/lowlevel_init.S
create mode 100644 include/configs/flea3.h
diff --git a/MAINTAINERS b/MAINTAINERS
index cd0dd91..804b899 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -560,6 +560,7 @@ Albert ARIBAUD <albert.u.boot@aribaud.net>
Stefano Babic <sbabic@denx.de>
ea20 davinci
+ flea3 i.MX35
mx35pdk i.MX35
mx51evk i.MX51
polaris xscale/pxa
diff --git a/board/CarMediaLab/flea3/Makefile b/board/CarMediaLab/flea3/Makefile
new file mode 100644
index 0000000..f5ad494
--- /dev/null
+++ b/board/CarMediaLab/flea3/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := flea3.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
new file mode 100644
index 0000000..64f4b57
--- /dev/null
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx35_pins.h>
+#include <asm/arch/iomux.h>
+#include <i2c.h>
+#include <linux/types.h>
+#include <asm/gpio.h>
+#include <asm/arch/sys_proto.h>
+#include <netdev.h>
+
+#ifndef CONFIG_BOARD_EARLY_INIT_F
+#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
+#endif
+
+#define CCM_CCMR_CONFIG 0x003F4208
+
+#define ESDCTL_DDR2_CONFIG 0x007FFC3F
+#define ESDCTL_0x92220000 0x92220000
+#define ESDCTL_0xA2220000 0xA2220000
+#define ESDCTL_0xB2220000 0xB2220000
+#define ESDCTL_0x82228080 0x82228080
+#define ESDCTL_DDR2_EMR2 0x04000000
+#define ESDCTL_DDR2_EMR3 0x06000000
+#define ESDCTL_PRECHARGE 0x00000400
+#define ESDCTL_DDR2_EN_DLL 0x02000400
+#define ESDCTL_DDR2_RESET_DLL 0x00000333
+#define ESDCTL_DDR2_MR 0x00000233
+#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
+#define ESDCTL_DELAY_LINE5 0x00F49F00
+
+static inline void dram_wait(unsigned int count)
+{
+ volatile unsigned int wait = count;
+
+ while (wait--)
+ ;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+static void board_setup_sdram_bank(u32 start_address)
+
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+ u32 *cfg_reg, *ctl_reg;
+ u32 val;
+
+ switch (start_address) {
+ case CSD0_BASE_ADDR:
+ cfg_reg = &esdc->esdcfg0;
+ ctl_reg = &esdc->esdctl0;
+ break;
+ case CSD1_BASE_ADDR:
+ cfg_reg = &esdc->esdcfg1;
+ ctl_reg = &esdc->esdctl1;
+ break;
+ default:
+ return;
+ }
+
+ /* Initialize MISC register for DDR2 */
+ val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
+ ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
+ writel(val, &esdc->esdmisc);
+ val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
+ writel(val, &esdc->esdmisc);
+
+ /*
+ * according to DDR2 specs, wait a while before
+ * the PRECHARGE_ALL command
+ */
+ dram_wait(0x20000);
+
+ /* Load DDR2 config and timing */
+ writel(ESDCTL_DDR2_CONFIG, cfg_reg);
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ ctl_reg);
+ writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+ /* Load mode */
+ writel(ESDCTL_0xB2220000,
+ ctl_reg);
+ writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
+ writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
+ writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+ writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
+
+ /* Precharge ALL */
+ writel(ESDCTL_0x92220000,
+ ctl_reg);
+ writel(0xda, start_address + ESDCTL_PRECHARGE);
+
+ /* Set mode auto refresh : at least two refresh are required */
+ writel(ESDCTL_0xA2220000,
+ ctl_reg);
+ writel(0xda, start_address);
+ writel(0xda, start_address);
+
+ writel(ESDCTL_0xB2220000,
+ ctl_reg);
+ writeb(0xda, start_address + ESDCTL_DDR2_MR);
+ writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
+
+ /* OCD mode exit */
+ writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
+
+ /* Set normal mode */
+ writel(ESDCTL_0x82228080,
+ ctl_reg);
+
+ dram_wait(0x20000);
+
+ /* Do not set delay lines, only for MDDR */
+}
+
+static void board_setup_sdram(void)
+{
+ struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
+
+ /* Initialize with default values both CSD0/1 */
+ writel(0x2000, &esdc->esdctl0);
+ writel(0x2000, &esdc->esdctl1);
+
+ board_setup_sdram_bank(CSD1_BASE_ADDR);
+}
+
+static void setup_iomux_uart3(void)
+{
+ mxc_request_iomux(MX35_PIN_RTS2_UART3_RXD_MUX, MUX_CONFIG_ALT7);
+ mxc_request_iomux(MX35_PIN_CTS2_UART3_TXD_MUX, MUX_CONFIG_ALT7);
+}
+
+static void setup_iomux_i2c(void)
+{
+ int pad;
+
+ mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
+
+ pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
+ | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
+
+ mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
+ mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
+
+ mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
+ mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
+
+ mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
+ mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
+}
+
+
+static void setup_iomux_spi(void)
+{
+ mxc_request_iomux(MX35_PIN_CSPI1_MOSI, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_MISO, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS0, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SS1, MUX_CONFIG_SION);
+ mxc_request_iomux(MX35_PIN_CSPI1_SCLK, MUX_CONFIG_SION);
+}
+
+static void setup_iomux_fec(void)
+{
+ /* setup pins for FEC */
+ mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC);
+ mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC);
+
+}
+
+int board_early_init_f(void)
+{
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ /* setup GPIO3_1 to set HighVCore signal */
+ mxc_request_iomux(MX35_PIN_ATA_DATA1, MUX_CONFIG_ALT5);
+ gpio_direction_output(65, 1);
+
+ /* initialize PLL and clock configuration */
+ writel(CCM_CCMR_CONFIG, &ccm->ccmr);
+
+ writel(CCM_MPLL_532_HZ, &ccm->mpctl);
+ writel(CCM_PPLL_300_HZ, &ccm->ppctl);
+
+ /* Set the core to run at 532 Mhz */
+ writel(0x00001000, &ccm->pdr0);
+
+ /* Set-up RAM */
+ board_setup_sdram();
+
+ /* enable clocks */
+ writel(readl(&ccm->cgr0) |
+ MXC_CCM_CGR0_EMI_MASK |
+ MXC_CCM_CGR0_EDI0_MASK |
+ MXC_CCM_CGR0_EPIT1_MASK,
+ &ccm->cgr0);
+
+ writel(readl(&ccm->cgr1) |
+ MXC_CCM_CGR1_FEC_MASK |
+ MXC_CCM_CGR1_GPIO1_MASK |
+ MXC_CCM_CGR1_GPIO2_MASK |
+ MXC_CCM_CGR1_GPIO3_MASK |
+ MXC_CCM_CGR1_I2C1_MASK |
+ MXC_CCM_CGR1_I2C2_MASK |
+ MXC_CCM_CGR1_I2C3_MASK,
+ &ccm->cgr1);
+
+ /* Set-up NAND */
+ __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
+
+ /* Set pinmux for the required peripherals */
+ setup_iomux_uart3();
+ setup_iomux_i2c();
+ setup_iomux_fec();
+ setup_iomux_spi();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = 0;
+
+ return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
+}
diff --git a/board/CarMediaLab/flea3/lowlevel_init.S b/board/CarMediaLab/flea3/lowlevel_init.S
new file mode 100644
index 0000000..2f42fc9
--- /dev/null
+++ b/board/CarMediaLab/flea3/lowlevel_init.S
@@ -0,0 +1,79 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm-offsets.h>
+#include <asm/arch/imx-regs.h>
+#include <generated/asm-offsets.h>
+
+/*
+ * Configuration for the flea3 board.
+ * These defines are used by the included macros and must
+ * be defined first
+ */
+#define AIPS_MPR_CONFIG 0x77777777
+#define AIPS_OPACR_CONFIG 0x00000000
+
+/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
+#define MAX_MPR_CONFIG 0x00302154
+
+/* SGPCR - always park on last master */
+#define MAX_SGPCR_CONFIG 0x00000010
+
+/* MGPCR - restore default values */
+#define MAX_MGPCR_CONFIG 0x00000000
+
+/*
+ * M3IF Control Register (M3IFCTL)
+ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
+ * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
+ * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
+ * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
+ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
+ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
+ * ------------
+ * 0x00000040
+ */
+#define M3IF_CONFIG 0x00000040
+
+#define CCM_PDR0_CONFIG 0x00801000
+
+/*
+ * includes MX35 utility macros
+ */
+#include <asm/arch/lowlevel_macro.S>
+
+.globl lowlevel_init
+lowlevel_init:
+
+ core_init
+
+ init_aips
+
+ init_max
+
+ init_m3if
+
+ mov pc, lr
diff --git a/boards.cfg b/boards.cfg
index da3c2a0..07865ad 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -42,6 +42,7 @@ imx31_litekit arm arm1136 - logicpd
imx31_phycore arm arm1136 - - mx31
imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET
mx31pdk arm arm1136 - freescale mx31 mx31pdk:NAND_U_BOOT
+flea3 arm arm1136 - CarMediaLab mx35
mx35pdk arm arm1136 - freescale mx35
mx35pdk_nand arm arm1136 mx35pdk freescale mx35 mx35pdk:NAND_U_BOOT
omap2420h4 arm arm1136 - ti omap24xx
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
new file mode 100644
index 0000000..d88c578
--- /dev/null
+++ b/include/configs/flea3.h
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
+ *
+ * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Configuration for the flea3 board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARM1136 /* This is an arm1136 CPU core */
+#define CONFIG_MX35
+#define CONFIG_MX35_HCLK_FREQ 24000000
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Only in case the value is not present in mach-types.h */
+#ifndef MACH_TYPE_FLEA3
+#define MACH_TYPE_FLEA3 3668
+#endif
+
+#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
+
+/* Set TEXT at the beginning of the NOR flash */
+#define CONFIG_SYS_TEXT_BASE 0xA0000000
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+/* This is required to setup the ESDC controller */
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_MX35_PORT3
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0xfe
+#define CONFIG_MXC_SPI
+#define CONFIG_MXC_GPIO
+
+/*
+ * UART (console)
+ */
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX35_UART3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/*
+ * Command definition
+ */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_DNS
+
+#define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_NET_RETRY_COUNT 100
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_FEC_MXC
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_MXC_PHYADDR 0x1
+
+#define CONFIG_MII
+#define CONFIG_DISCOVER_PHY
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "flea3 U-Boot > "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ 1000
+
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD1_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE CSD1_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000)
+#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_GBL_DATA_OFFSET)
+
+/*
+ * MTD Command for mtdparts
+ */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=mxc_nand,nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT "mtdparts=mxc_nand:196m(root1)," \
+ "196m(root2),-(user);" \
+ "physmap-flash.0:512k(u-boot),64k(env1)," \
+ "64k(env2),3776k(kernel1),3776k(kernel2)"
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+/* Monitor at beginning of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+
+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
+ CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_ENV_IS_IN_FLASH
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
+#define CONFIG_FLASH_CFI_DRIVER
+
+/* A non-standard buffered write algorithm */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* faster */
+#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
+
+/*
+ * NAND FLASH driver setup
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
+
+/*
+ * Default environment and default scripts
+ * to update uboot and load kernel
+ */
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_HOSTNAME flea3
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip_sta=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
+ "addip=if test -n ${ipdyn};then run addip_dyn;" \
+ "else run addip_sta;fi\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "addtty=setenv bootargs ${bootargs}" \
+ " console=ttymxc0,${baudrate}\0" \
+ "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
+ "loadaddr=90800000\0" \
+ "kernel_addr_r=90800000\0" \
+ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "flash_self=run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
+ "run nfsargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r}\0" \
+ "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
+ "net_self=if run net_self_load;then " \
+ "run ramargs addip addtty addmtd addmisc;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
+ "else echo Images not loades;fi\0" \
+ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "load=tftp ${loadaddr} ${u-boot}\0" \
+ "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "update=protect off ${uboot_addr} +40000;" \
+ "erase ${uboot_addr} +40000;" \
+ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+ "upd=if run load;then echo Updating u-boot;if run update;" \
+ "then echo U-Boot updated;" \
+ "else echo Error updating u-boot !;" \
+ "echo Board without bootloader !!;" \
+ "fi;" \
+ "else echo U-Boot not downloaded..exiting;fi\0" \
+ "bootcmd=run net_nfs\0"
+
+#endif /* __CONFIG_H */
--
1.7.1
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