* [PATCH V3 0/4]: ARM: SAMSUNG: Add SPI clkdev support
@ 2011-10-10 8:03 ` Padmavathi Venna
0 siblings, 0 replies; 14+ messages in thread
From: Padmavathi Venna @ 2011-10-10 8:03 UTC (permalink / raw)
To: linux-arm-kernel
This patchset modifies the existing clkdev to make SPI driver
independent of the clock names send from platform data. This
patches enables the SPI driver to request SPI bus clocks
using generic connection ID.
V1 patch series are:
http://www.spinics.net/lists/arm-kernel/msg141671.html
Changes since V1:
-Add newly introduced CLKDEV_INIT macro for creating clk_lookup
structure as suggested by Russell King
V2 patches series are:
http://www.spinics.net/lists/arm-kernel/msg142733.html
Changes since V2:
-Reworked the patches as per the following link. Patch series in
the following link removed & and , from the macro declaration and added
in the macro defination.
http://www.spinics.net/lists/arm-kernel/msg143663.html
Padmavathi Venna (4):
ARM: S3C64XX: Add SPI clkdev support
ARM: S5PC100: Add SPI clkdev support
ARM: S5P64X0: Add SPI clkdev support
ARM: S5PV210: Add SPI clkdev support
arch/arm/mach-s3c64xx/clock.c | 98 ++++++++++++++++--------
arch/arm/mach-s5p64x0/clock-s5p6440.c | 57 +++++++++-----
arch/arm/mach-s5p64x0/clock-s5p6450.c | 57 +++++++++-----
arch/arm/mach-s5pc100/clock.c | 132 ++++++++++++++++++++-------------
arch/arm/mach-s5pv210/clock.c | 58 ++++++++++-----
5 files changed, 259 insertions(+), 143 deletions(-)
--
1.7.4.4
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V3 1/4] ARM: S3C64XX: Add SPI clkdev support
2011-10-10 8:03 ` Padmavathi Venna
@ 2011-10-10 8:03 ` Padmavathi Venna
-1 siblings, 0 replies; 14+ messages in thread
From: Padmavathi Venna @ 2011-10-10 8:03 UTC (permalink / raw)
To: padma.v, padma.kvr, linux-samsung-soc, linux-arm-kernel
Cc: ben-linux, linux, kgene.kim
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
arch/arm/mach-s3c64xx/clock.c | 98 +++++++++++++++++++++++++++-------------
1 files changed, 66 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 39c238d..3420e5c 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = {
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, {
- .name = "spi_48m",
- .devname = "s3c64xx-spi.0",
- .parent = &clk_48m,
- .enable = s3c64xx_sclk_ctrl,
- .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
- }, {
- .name = "spi_48m",
- .devname = "s3c64xx-spi.1",
- .parent = &clk_48m,
- .enable = s3c64xx_sclk_ctrl,
- .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
- }, {
.name = "48m",
.devname = "s3c-sdhci.0",
.parent = &clk_48m,
@@ -625,26 +613,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
.sources = &clkset_uart,
}, {
-/* Where does UCLK0 come from? */
- .clk = {
- .name = "spi-bus",
- .devname = "s3c64xx-spi.0",
- .ctrlbit = S3C_CLKCON_SCLK_SPI0,
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
- .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
- .sources = &clkset_spi_mmc,
- }, {
- .clk = {
- .name = "spi-bus",
- .devname = "s3c64xx-spi.1",
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
- .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
- .sources = &clkset_spi_mmc,
- }, {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.0",
@@ -695,6 +663,60 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clk clk_48m_spi0 = {
+ .name = "spi_48m",
+ .parent = &clk_48m,
+ .enable = s3c64xx_sclk_ctrl,
+ .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
+};
+
+static struct clk clk_48m_spi1 = {
+ .name = "spi_48m",
+ .parent = &clk_48m,
+ .enable = s3c64xx_sclk_ctrl,
+ .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
+};
+
+static struct clksrc_clk sclk_spi0 = {
+ .clk = {
+ .name = "spi-bus",
+ .ctrlbit = S3C_CLKCON_SCLK_SPI0,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
+ .sources = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk sclk_spi1 = {
+ .clk = {
+ .name = "spi-bus",
+ .ctrlbit = S3C_CLKCON_SCLK_SPI1,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
+ .sources = &clkset_spi_mmc,
+};
+
+static struct clk_lookup clk_lookup_table[] = {
+ CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &sclk_spi0.clk),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &sclk_spi1.clk),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &sclk_spi0,
+ &sclk_spi1,
+};
+
+static struct clk *clk_cdev[] = {
+ &clk_48m_spi0,
+ &clk_48m_spi1,
+};
+
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
@@ -811,11 +833,16 @@ static struct clk *clks[] __initdata = {
void __init s3c64xx_register_clocks(unsigned long xtal,
unsigned armclk_divlimit)
{
+ int ptr;
+
armclk_mask = armclk_divlimit;
s3c24xx_register_baseclocks(xtal);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
@@ -823,5 +850,12 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+ s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+ s3c_disable_clocks(clk_cdev[ptr], 1);
+
s3c_pwmclk_init();
+
+ clkdev_add_table(clk_lookup_table, ARRAY_SIZE(clk_lookup_table));
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V3 1/4] ARM: S3C64XX: Add SPI clkdev support
@ 2011-10-10 8:03 ` Padmavathi Venna
0 siblings, 0 replies; 14+ messages in thread
From: Padmavathi Venna @ 2011-10-10 8:03 UTC (permalink / raw)
To: linux-arm-kernel
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
arch/arm/mach-s3c64xx/clock.c | 98 +++++++++++++++++++++++++++-------------
1 files changed, 66 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 39c238d..3420e5c 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = {
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, {
- .name = "spi_48m",
- .devname = "s3c64xx-spi.0",
- .parent = &clk_48m,
- .enable = s3c64xx_sclk_ctrl,
- .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
- }, {
- .name = "spi_48m",
- .devname = "s3c64xx-spi.1",
- .parent = &clk_48m,
- .enable = s3c64xx_sclk_ctrl,
- .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
- }, {
.name = "48m",
.devname = "s3c-sdhci.0",
.parent = &clk_48m,
@@ -625,26 +613,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
.sources = &clkset_uart,
}, {
-/* Where does UCLK0 come from? */
- .clk = {
- .name = "spi-bus",
- .devname = "s3c64xx-spi.0",
- .ctrlbit = S3C_CLKCON_SCLK_SPI0,
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
- .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
- .sources = &clkset_spi_mmc,
- }, {
- .clk = {
- .name = "spi-bus",
- .devname = "s3c64xx-spi.1",
- .enable = s3c64xx_sclk_ctrl,
- },
- .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
- .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
- .sources = &clkset_spi_mmc,
- }, {
.clk = {
.name = "audio-bus",
.devname = "samsung-i2s.0",
@@ -695,6 +663,60 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clk clk_48m_spi0 = {
+ .name = "spi_48m",
+ .parent = &clk_48m,
+ .enable = s3c64xx_sclk_ctrl,
+ .ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
+};
+
+static struct clk clk_48m_spi1 = {
+ .name = "spi_48m",
+ .parent = &clk_48m,
+ .enable = s3c64xx_sclk_ctrl,
+ .ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
+};
+
+static struct clksrc_clk sclk_spi0 = {
+ .clk = {
+ .name = "spi-bus",
+ .ctrlbit = S3C_CLKCON_SCLK_SPI0,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
+ .sources = &clkset_spi_mmc,
+};
+
+static struct clksrc_clk sclk_spi1 = {
+ .clk = {
+ .name = "spi-bus",
+ .ctrlbit = S3C_CLKCON_SCLK_SPI1,
+ .enable = s3c64xx_sclk_ctrl,
+ },
+ .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
+ .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
+ .sources = &clkset_spi_mmc,
+};
+
+static struct clk_lookup clk_lookup_table[] = {
+ CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &sclk_spi0.clk),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &sclk_spi1.clk),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &sclk_spi0,
+ &sclk_spi1,
+};
+
+static struct clk *clk_cdev[] = {
+ &clk_48m_spi0,
+ &clk_48m_spi1,
+};
+
/* Clock initialisation code */
static struct clksrc_clk *init_parents[] = {
@@ -811,11 +833,16 @@ static struct clk *clks[] __initdata = {
void __init s3c64xx_register_clocks(unsigned long xtal,
unsigned armclk_divlimit)
{
+ int ptr;
+
armclk_mask = armclk_divlimit;
s3c24xx_register_baseclocks(xtal);
s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
@@ -823,5 +850,12 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+ s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+ s3c_disable_clocks(clk_cdev[ptr], 1);
+
s3c_pwmclk_init();
+
+ clkdev_add_table(clk_lookup_table, ARRAY_SIZE(clk_lookup_table));
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH V3 2/4] ARM: S5PC100: Add SPI clkdev support
2011-10-10 8:03 ` Padmavathi Venna
@ 2011-10-10 8:03 ` Padmavathi Venna
-1 siblings, 0 replies; 14+ messages in thread
From: Padmavathi Venna @ 2011-10-10 8:03 UTC (permalink / raw)
To: padma.v, padma.kvr, linux-samsung-soc, linux-arm-kernel
Cc: ben-linux, linux, kgene.kim
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
arch/arm/mach-s5pc100/clock.c | 132 +++++++++++++++++++++++++----------------
1 files changed, 81 insertions(+), 51 deletions(-)
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 8d47709..e025be7 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -673,24 +673,6 @@ static struct clk init_clocks_off[] = {
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 8),
}, {
- .name = "spi_48m",
- .devname = "s3c64xx-spi.0",
- .parent = &clk_mout_48m.clk,
- .enable = s5pc100_sclk0_ctrl,
- .ctrlbit = (1 << 7),
- }, {
- .name = "spi_48m",
- .devname = "s3c64xx-spi.1",
- .parent = &clk_mout_48m.clk,
- .enable = s5pc100_sclk0_ctrl,
- .ctrlbit = (1 << 8),
- }, {
- .name = "spi_48m",
- .devname = "s3c64xx-spi.2",
- .parent = &clk_mout_48m.clk,
- .enable = s5pc100_sclk0_ctrl,
- .ctrlbit = (1 << 9),
- }, {
.name = "mmc_48m",
.devname = "s3c-sdhci.0",
.parent = &clk_mout_48m.clk,
@@ -929,39 +911,6 @@ static struct clksrc_clk clk_sclk_spdif = {
static struct clksrc_clk clksrcs[] = {
{
.clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
- .ctrlbit = (1 << 4),
- .enable = s5pc100_sclk0_ctrl,
-
- },
- .sources = &clk_src_group1,
- .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
- .ctrlbit = (1 << 5),
- .enable = s5pc100_sclk0_ctrl,
-
- },
- .sources = &clk_src_group1,
- .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.2",
- .ctrlbit = (1 << 6),
- .enable = s5pc100_sclk0_ctrl,
-
- },
- .sources = &clk_src_group1,
- .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
- }, {
- .clk = {
.name = "uclk1",
.ctrlbit = (1 << 3),
.enable = s5pc100_sclk0_ctrl,
@@ -1098,6 +1047,78 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clk clk_48m_spi0 = {
+ .name = "spi_48m",
+ .parent = &clk_mout_48m.clk,
+ .enable = s5pc100_sclk0_ctrl,
+ .ctrlbit = (1 << 7),
+};
+
+static struct clk clk_48m_spi1 = {
+ .name = "spi_48m",
+ .parent = &clk_mout_48m.clk,
+ .enable = s5pc100_sclk0_ctrl,
+ .ctrlbit = (1 << 8),
+};
+
+static struct clk clk_48m_spi2 = {
+ .name = "spi_48m",
+ .parent = &clk_mout_48m.clk,
+ .enable = s5pc100_sclk0_ctrl,
+ .ctrlbit = (1 << 9),
+};
+
+static struct clksrc_clk sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 4),
+ .enable = s5pc100_sclk0_ctrl,
+ },
+ .sources = &clk_src_group1,
+ .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 5),
+ .enable = s5pc100_sclk0_ctrl,
+ },
+ .sources = &clk_src_group1,
+ .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk sclk_spi2 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 6),
+ .enable = s5pc100_sclk0_ctrl,
+ },
+ .sources = &clk_src_group1,
+ .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
+};
+
+static struct clk_lookup clk_lookup_table[] = {
+ CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &sclk_spi0.clk),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &sclk_spi1.clk),
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &sclk_spi0,
+ &sclk_spi1,
+};
+
+static struct clk *clk_cdev[] = {
+ &clk_48m_spi0,
+ &clk_48m_spi1,
+};
+
/* Clock initialisation code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -1276,12 +1297,21 @@ void __init s5pc100_register_clocks(void)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+ s3c_disable_clocks(clk_cdev[ptr], 1);
+
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
+ clkdev_add_table(clk_lookup_table, ARRAY_SIZE(clk_lookup_table));
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V3 2/4] ARM: S5PC100: Add SPI clkdev support
@ 2011-10-10 8:03 ` Padmavathi Venna
0 siblings, 0 replies; 14+ messages in thread
From: Padmavathi Venna @ 2011-10-10 8:03 UTC (permalink / raw)
To: linux-arm-kernel
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
arch/arm/mach-s5pc100/clock.c | 132 +++++++++++++++++++++++++----------------
1 files changed, 81 insertions(+), 51 deletions(-)
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 8d47709..e025be7 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -673,24 +673,6 @@ static struct clk init_clocks_off[] = {
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 8),
}, {
- .name = "spi_48m",
- .devname = "s3c64xx-spi.0",
- .parent = &clk_mout_48m.clk,
- .enable = s5pc100_sclk0_ctrl,
- .ctrlbit = (1 << 7),
- }, {
- .name = "spi_48m",
- .devname = "s3c64xx-spi.1",
- .parent = &clk_mout_48m.clk,
- .enable = s5pc100_sclk0_ctrl,
- .ctrlbit = (1 << 8),
- }, {
- .name = "spi_48m",
- .devname = "s3c64xx-spi.2",
- .parent = &clk_mout_48m.clk,
- .enable = s5pc100_sclk0_ctrl,
- .ctrlbit = (1 << 9),
- }, {
.name = "mmc_48m",
.devname = "s3c-sdhci.0",
.parent = &clk_mout_48m.clk,
@@ -929,39 +911,6 @@ static struct clksrc_clk clk_sclk_spdif = {
static struct clksrc_clk clksrcs[] = {
{
.clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
- .ctrlbit = (1 << 4),
- .enable = s5pc100_sclk0_ctrl,
-
- },
- .sources = &clk_src_group1,
- .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
- .ctrlbit = (1 << 5),
- .enable = s5pc100_sclk0_ctrl,
-
- },
- .sources = &clk_src_group1,
- .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.2",
- .ctrlbit = (1 << 6),
- .enable = s5pc100_sclk0_ctrl,
-
- },
- .sources = &clk_src_group1,
- .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
- .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
- }, {
- .clk = {
.name = "uclk1",
.ctrlbit = (1 << 3),
.enable = s5pc100_sclk0_ctrl,
@@ -1098,6 +1047,78 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clk clk_48m_spi0 = {
+ .name = "spi_48m",
+ .parent = &clk_mout_48m.clk,
+ .enable = s5pc100_sclk0_ctrl,
+ .ctrlbit = (1 << 7),
+};
+
+static struct clk clk_48m_spi1 = {
+ .name = "spi_48m",
+ .parent = &clk_mout_48m.clk,
+ .enable = s5pc100_sclk0_ctrl,
+ .ctrlbit = (1 << 8),
+};
+
+static struct clk clk_48m_spi2 = {
+ .name = "spi_48m",
+ .parent = &clk_mout_48m.clk,
+ .enable = s5pc100_sclk0_ctrl,
+ .ctrlbit = (1 << 9),
+};
+
+static struct clksrc_clk sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 4),
+ .enable = s5pc100_sclk0_ctrl,
+ },
+ .sources = &clk_src_group1,
+ .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 5),
+ .enable = s5pc100_sclk0_ctrl,
+ },
+ .sources = &clk_src_group1,
+ .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk sclk_spi2 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 6),
+ .enable = s5pc100_sclk0_ctrl,
+ },
+ .sources = &clk_src_group1,
+ .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
+ .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
+};
+
+static struct clk_lookup clk_lookup_table[] = {
+ CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &sclk_spi0.clk),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &sclk_spi1.clk),
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &sclk_spi0,
+ &sclk_spi1,
+};
+
+static struct clk *clk_cdev[] = {
+ &clk_48m_spi0,
+ &clk_48m_spi1,
+};
+
/* Clock initialisation code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -1276,12 +1297,21 @@ void __init s5pc100_register_clocks(void)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+ s3c_disable_clocks(clk_cdev[ptr], 1);
+
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
+ clkdev_add_table(clk_lookup_table, ARRAY_SIZE(clk_lookup_table));
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH V3 3/4] ARM: S5P64X0: Add SPI clkdev support
2011-10-10 8:03 ` Padmavathi Venna
@ 2011-10-10 8:03 ` Padmavathi Venna
-1 siblings, 0 replies; 14+ messages in thread
From: Padmavathi Venna @ 2011-10-10 8:03 UTC (permalink / raw)
To: padma.v, padma.kvr, linux-samsung-soc, linux-arm-kernel
Cc: ben-linux, linux, kgene.kim
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
arch/arm/mach-s5p64x0/clock-s5p6440.c | 57 +++++++++++++++++++++-----------
arch/arm/mach-s5p64x0/clock-s5p6450.c | 57 +++++++++++++++++++++-----------
2 files changed, 74 insertions(+), 40 deletions(-)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index c54c65d..9e4f517 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -430,26 +430,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
}, {
.clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
- .ctrlbit = (1 << 20),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = &clkset_group1,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
- .ctrlbit = (1 << 21),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = &clkset_group1,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
- }, {
- .clk = {
.name = "sclk_post",
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
@@ -487,6 +467,39 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clksrc_clk sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 20),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = &clkset_group1,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 21),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = &clkset_group1,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
+static struct clk_lookup clk_lookup_table[] = {
+ CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &sclk_spi0.clk),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &sclk_spi1.clk),
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &sclk_spi0,
+ &sclk_spi1,
+};
+
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -581,6 +594,9 @@ void __init s5p6440_register_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
@@ -590,4 +606,5 @@ void __init s5p6440_register_clocks(void)
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
+ clkdev_add_table(clk_lookup_table, ARRAY_SIZE(clk_lookup_table));
}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 2d04abf..323c30c 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -452,26 +452,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
}, {
.clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
- .ctrlbit = (1 << 20),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
- .ctrlbit = (1 << 21),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
- }, {
- .clk = {
.name = "sclk_fimc",
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
@@ -536,6 +516,39 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clksrc_clk sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 20),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 21),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
+static struct clk_lookup clk_lookup_table[] = {
+ CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &sclk_spi0.clk),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &sclk_spi1.clk),
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &sclk_spi0,
+ &sclk_spi1,
+};
+
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -632,6 +645,9 @@ void __init s5p6450_register_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
@@ -641,4 +657,5 @@ void __init s5p6450_register_clocks(void)
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
+ clkdev_add_table(clk_lookup_table, ARRAY_SIZE(clk_lookup_table));
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V3 3/4] ARM: S5P64X0: Add SPI clkdev support
@ 2011-10-10 8:03 ` Padmavathi Venna
0 siblings, 0 replies; 14+ messages in thread
From: Padmavathi Venna @ 2011-10-10 8:03 UTC (permalink / raw)
To: linux-arm-kernel
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
arch/arm/mach-s5p64x0/clock-s5p6440.c | 57 +++++++++++++++++++++-----------
arch/arm/mach-s5p64x0/clock-s5p6450.c | 57 +++++++++++++++++++++-----------
2 files changed, 74 insertions(+), 40 deletions(-)
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index c54c65d..9e4f517 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -430,26 +430,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
}, {
.clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
- .ctrlbit = (1 << 20),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = &clkset_group1,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
- .ctrlbit = (1 << 21),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = &clkset_group1,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
- }, {
- .clk = {
.name = "sclk_post",
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
@@ -487,6 +467,39 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clksrc_clk sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 20),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = &clkset_group1,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 21),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = &clkset_group1,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
+static struct clk_lookup clk_lookup_table[] = {
+ CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &sclk_spi0.clk),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &sclk_spi1.clk),
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &sclk_spi0,
+ &sclk_spi1,
+};
+
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -581,6 +594,9 @@ void __init s5p6440_register_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
@@ -590,4 +606,5 @@ void __init s5p6440_register_clocks(void)
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
+ clkdev_add_table(clk_lookup_table, ARRAY_SIZE(clk_lookup_table));
}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 2d04abf..323c30c 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -452,26 +452,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
}, {
.clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
- .ctrlbit = (1 << 20),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
- .ctrlbit = (1 << 21),
- .enable = s5p64x0_sclk_ctrl,
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
- .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
- }, {
- .clk = {
.name = "sclk_fimc",
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
@@ -536,6 +516,39 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clksrc_clk sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 20),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .ctrlbit = (1 << 21),
+ .enable = s5p64x0_sclk_ctrl,
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+ .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+};
+
+static struct clk_lookup clk_lookup_table[] = {
+ CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &sclk_spi0.clk),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &sclk_spi1.clk),
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &sclk_spi0,
+ &sclk_spi1,
+};
+
/* Clock initialization code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -632,6 +645,9 @@ void __init s5p6450_register_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
@@ -641,4 +657,5 @@ void __init s5p6450_register_clocks(void)
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
+ clkdev_add_table(clk_lookup_table, ARRAY_SIZE(clk_lookup_table));
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH V3 4/4] ARM: S5PV210: Add SPI clkdev support
2011-10-10 8:03 ` Padmavathi Venna
@ 2011-10-10 8:03 ` Padmavathi Venna
-1 siblings, 0 replies; 14+ messages in thread
From: Padmavathi Venna @ 2011-10-10 8:03 UTC (permalink / raw)
To: padma.v, padma.kvr, linux-samsung-soc, linux-arm-kernel
Cc: ben-linux, linux, kgene.kim
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
arch/arm/mach-s5pv210/clock.c | 58 ++++++++++++++++++++++++++--------------
1 files changed, 38 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 4c5ac7a..3edf034 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -983,26 +983,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
}, {
.clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 16),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 17),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
- }, {
- .clk = {
.name = "sclk_pwi",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 29),
@@ -1022,6 +1002,39 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clksrc_clk sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 17),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
+};
+
+static struct clk_lookup clk_lookup_table[] = {
+ CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &sclk_spi0.clk),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &sclk_spi1.clk),
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &sclk_spi0,
+ &sclk_spi1,
+};
+
/* Clock initialisation code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -1273,6 +1286,9 @@ void __init s5pv210_register_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
s3c_register_clksrc(sclk_tv[ptr], 1);
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
@@ -1281,4 +1297,6 @@ void __init s5pv210_register_clocks(void)
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
+
+ clkdev_add_table(clk_lookup_table, ARRAY_SIZE(clk_lookup_table));
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH V3 4/4] ARM: S5PV210: Add SPI clkdev support
@ 2011-10-10 8:03 ` Padmavathi Venna
0 siblings, 0 replies; 14+ messages in thread
From: Padmavathi Venna @ 2011-10-10 8:03 UTC (permalink / raw)
To: linux-arm-kernel
Registered the SPI bus clocks with clkdev using generic
connection id.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
---
arch/arm/mach-s5pv210/clock.c | 58 ++++++++++++++++++++++++++--------------
1 files changed, 38 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 4c5ac7a..3edf034 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -983,26 +983,6 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
}, {
.clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.0",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 16),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
- }, {
- .clk = {
- .name = "sclk_spi",
- .devname = "s3c64xx-spi.1",
- .enable = s5pv210_clk_mask0_ctrl,
- .ctrlbit = (1 << 17),
- },
- .sources = &clkset_group2,
- .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
- .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
- }, {
- .clk = {
.name = "sclk_pwi",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 29),
@@ -1022,6 +1002,39 @@ static struct clksrc_clk clksrcs[] = {
},
};
+static struct clksrc_clk sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .enable = s5pv210_clk_mask0_ctrl,
+ .ctrlbit = (1 << 17),
+ },
+ .sources = &clkset_group2,
+ .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
+ .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
+};
+
+static struct clk_lookup clk_lookup_table[] = {
+ CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+ CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &sclk_spi0.clk),
+ CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &sclk_spi1.clk),
+};
+
+static struct clksrc_clk *clksrc_cdev[] = {
+ &sclk_spi0,
+ &sclk_spi1,
+};
+
/* Clock initialisation code */
static struct clksrc_clk *sysclks[] = {
&clk_mout_apll,
@@ -1273,6 +1286,9 @@ void __init s5pv210_register_clocks(void)
for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
s3c_register_clksrc(sclk_tv[ptr], 1);
+ for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+ s3c_register_clksrc(clksrc_cdev[ptr], 1);
+
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
@@ -1281,4 +1297,6 @@ void __init s5pv210_register_clocks(void)
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
+
+ clkdev_add_table(clk_lookup_table, ARRAY_SIZE(clk_lookup_table));
}
--
1.7.4.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* RE: [PATCH V3 0/4]: ARM: SAMSUNG: Add SPI clkdev support
2011-10-10 8:03 ` Padmavathi Venna
@ 2011-10-10 9:42 ` Kukjin Kim
-1 siblings, 0 replies; 14+ messages in thread
From: Kukjin Kim @ 2011-10-10 9:42 UTC (permalink / raw)
To: 'Padmavathi Venna', padma.kvr, linux-samsung-soc,
linux-arm-kernel
Cc: ben-linux, linux
Padmavathi Venna wrote:
>
> This patchset modifies the existing clkdev to make SPI driver
> independent of the clock names send from platform data. This
> patches enables the SPI driver to request SPI bus clocks
> using generic connection ID.
>
> V1 patch series are:
> http://www.spinics.net/lists/arm-kernel/msg141671.html
>
> Changes since V1:
> -Add newly introduced CLKDEV_INIT macro for creating clk_lookup
> structure as suggested by Russell King
> V2 patches series are:
> http://www.spinics.net/lists/arm-kernel/msg142733.html
>
> Changes since V2:
> -Reworked the patches as per the following link. Patch series in
> the following link removed & and , from the macro declaration and
added
> in the macro defination.
> http://www.spinics.net/lists/arm-kernel/msg143663.html
>
> Padmavathi Venna (4):
> ARM: S3C64XX: Add SPI clkdev support
> ARM: S5PC100: Add SPI clkdev support
> ARM: S5P64X0: Add SPI clkdev support
> ARM: S5PV210: Add SPI clkdev support
>
> arch/arm/mach-s3c64xx/clock.c | 98 ++++++++++++++++--------
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 57 +++++++++-----
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 57 +++++++++-----
> arch/arm/mach-s5pc100/clock.c | 132 ++++++++++++++++++++--------
> -----
> arch/arm/mach-s5pv210/clock.c | 58 ++++++++++-----
> 5 files changed, 259 insertions(+), 143 deletions(-)
>
> --
> 1.7.4.4
Looks ok but this needs 'CLKDEV_INIT' patch. Please wait until it can be
sent to upstream for this patch.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V3 0/4]: ARM: SAMSUNG: Add SPI clkdev support
@ 2011-10-10 9:42 ` Kukjin Kim
0 siblings, 0 replies; 14+ messages in thread
From: Kukjin Kim @ 2011-10-10 9:42 UTC (permalink / raw)
To: linux-arm-kernel
Padmavathi Venna wrote:
>
> This patchset modifies the existing clkdev to make SPI driver
> independent of the clock names send from platform data. This
> patches enables the SPI driver to request SPI bus clocks
> using generic connection ID.
>
> V1 patch series are:
> http://www.spinics.net/lists/arm-kernel/msg141671.html
>
> Changes since V1:
> -Add newly introduced CLKDEV_INIT macro for creating clk_lookup
> structure as suggested by Russell King
> V2 patches series are:
> http://www.spinics.net/lists/arm-kernel/msg142733.html
>
> Changes since V2:
> -Reworked the patches as per the following link. Patch series in
> the following link removed & and , from the macro declaration and
added
> in the macro defination.
> http://www.spinics.net/lists/arm-kernel/msg143663.html
>
> Padmavathi Venna (4):
> ARM: S3C64XX: Add SPI clkdev support
> ARM: S5PC100: Add SPI clkdev support
> ARM: S5P64X0: Add SPI clkdev support
> ARM: S5PV210: Add SPI clkdev support
>
> arch/arm/mach-s3c64xx/clock.c | 98 ++++++++++++++++--------
> arch/arm/mach-s5p64x0/clock-s5p6440.c | 57 +++++++++-----
> arch/arm/mach-s5p64x0/clock-s5p6450.c | 57 +++++++++-----
> arch/arm/mach-s5pc100/clock.c | 132 ++++++++++++++++++++--------
> -----
> arch/arm/mach-s5pv210/clock.c | 58 ++++++++++-----
> 5 files changed, 259 insertions(+), 143 deletions(-)
>
> --
> 1.7.4.4
Looks ok but this needs 'CLKDEV_INIT' patch. Please wait until it can be
sent to upstream for this patch.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH V3 0/4]: ARM: SAMSUNG: Add SPI clkdev support
2011-10-10 9:42 ` Kukjin Kim
@ 2011-10-24 15:19 ` Kukjin Kim
-1 siblings, 0 replies; 14+ messages in thread
From: Kukjin Kim @ 2011-10-24 15:19 UTC (permalink / raw)
To: Kukjin Kim
Cc: 'Padmavathi Venna', padma.kvr, linux-samsung-soc,
linux-arm-kernel, ben-linux, linux
On 10/10/11 11:42, Kukjin Kim wrote:
> Padmavathi Venna wrote:
>>
>> This patchset modifies the existing clkdev to make SPI driver
>> independent of the clock names send from platform data. This
>> patches enables the SPI driver to request SPI bus clocks
>> using generic connection ID.
>>
>> V1 patch series are:
>> http://www.spinics.net/lists/arm-kernel/msg141671.html
>>
>> Changes since V1:
>> -Add newly introduced CLKDEV_INIT macro for creating clk_lookup
>> structure as suggested by Russell King
>> V2 patches series are:
>> http://www.spinics.net/lists/arm-kernel/msg142733.html
>>
>> Changes since V2:
>> -Reworked the patches as per the following link. Patch series in
>> the following link removed& and , from the macro declaration and
> added
>> in the macro defination.
>> http://www.spinics.net/lists/arm-kernel/msg143663.html
>>
>> Padmavathi Venna (4):
>> ARM: S3C64XX: Add SPI clkdev support
>> ARM: S5PC100: Add SPI clkdev support
>> ARM: S5P64X0: Add SPI clkdev support
>> ARM: S5PV210: Add SPI clkdev support
>>
>> arch/arm/mach-s3c64xx/clock.c | 98 ++++++++++++++++--------
>> arch/arm/mach-s5p64x0/clock-s5p6440.c | 57 +++++++++-----
>> arch/arm/mach-s5p64x0/clock-s5p6450.c | 57 +++++++++-----
>> arch/arm/mach-s5pc100/clock.c | 132 ++++++++++++++++++++--------
>> -----
>> arch/arm/mach-s5pv210/clock.c | 58 ++++++++++-----
>> 5 files changed, 259 insertions(+), 143 deletions(-)
>>
>> --
>> 1.7.4.4
> Looks ok but this needs 'CLKDEV_INIT' patch. Please wait until it can be
> sent to upstream for this patch.
>
Padmavathi,
As I said, this looks ok and can be applied now.
Could you please rework this based on my next-samsung-dt branch which
includes device tree patches so that I can apply this easily for v3.2?
If any problems, please let me know.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH V3 0/4]: ARM: SAMSUNG: Add SPI clkdev support
@ 2011-10-24 15:19 ` Kukjin Kim
0 siblings, 0 replies; 14+ messages in thread
From: Kukjin Kim @ 2011-10-24 15:19 UTC (permalink / raw)
To: linux-arm-kernel
On 10/10/11 11:42, Kukjin Kim wrote:
> Padmavathi Venna wrote:
>>
>> This patchset modifies the existing clkdev to make SPI driver
>> independent of the clock names send from platform data. This
>> patches enables the SPI driver to request SPI bus clocks
>> using generic connection ID.
>>
>> V1 patch series are:
>> http://www.spinics.net/lists/arm-kernel/msg141671.html
>>
>> Changes since V1:
>> -Add newly introduced CLKDEV_INIT macro for creating clk_lookup
>> structure as suggested by Russell King
>> V2 patches series are:
>> http://www.spinics.net/lists/arm-kernel/msg142733.html
>>
>> Changes since V2:
>> -Reworked the patches as per the following link. Patch series in
>> the following link removed& and , from the macro declaration and
> added
>> in the macro defination.
>> http://www.spinics.net/lists/arm-kernel/msg143663.html
>>
>> Padmavathi Venna (4):
>> ARM: S3C64XX: Add SPI clkdev support
>> ARM: S5PC100: Add SPI clkdev support
>> ARM: S5P64X0: Add SPI clkdev support
>> ARM: S5PV210: Add SPI clkdev support
>>
>> arch/arm/mach-s3c64xx/clock.c | 98 ++++++++++++++++--------
>> arch/arm/mach-s5p64x0/clock-s5p6440.c | 57 +++++++++-----
>> arch/arm/mach-s5p64x0/clock-s5p6450.c | 57 +++++++++-----
>> arch/arm/mach-s5pc100/clock.c | 132 ++++++++++++++++++++--------
>> -----
>> arch/arm/mach-s5pv210/clock.c | 58 ++++++++++-----
>> 5 files changed, 259 insertions(+), 143 deletions(-)
>>
>> --
>> 1.7.4.4
> Looks ok but this needs 'CLKDEV_INIT' patch. Please wait until it can be
> sent to upstream for this patch.
>
Padmavathi,
As I said, this looks ok and can be applied now.
Could you please rework this based on my next-samsung-dt branch which
includes device tree patches so that I can apply this easily for v3.2?
If any problems, please let me know.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <kgene.kim@samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.
^ permalink raw reply [flat|nested] 14+ messages in thread