Re: [PATCH] libxl: allow to enable/disable cpuid bits

[Christoph Egger <Christoph.Egger@amd.com>]

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On 11/02/11 11:20, Tim Deegan wrote:
> At 10:23 +0100 on 02 Nov (1320229392), Christoph Egger wrote:
>> On 11/01/11 20:07, Ian Jackson wrote:
>>> Christoph Egger writes ("[Xen-devel] [PATCH] libxl: allow to
>>> enable/disable cpuid bits"):
>>>>
>>>> Allow to enable/disable SVM specific cpuid bits
>>>> in the guest config file via cpuid config option.
>>>> Also allow to enable/disable the hypervisor cpuid bit
>>>> in the guest config file. We need to disable the
>>>> hypervisor cpuid bit to get Hyper-V going.
>>>
>>> The change itself looks plausible to me.  However I don't know much
>>> about cpuid; can you get an ack from a hypervisor maintainer or an
>>> suitable expert ?
>>
>> Keir? Tim?
>
> I think the hypervisor bit should be given a better name than 'raz' --
> although it is read-as-zero on real hardware that doesn't distinguish it
> from other raz bits, or describe what it does.
>
> 'hypervisor' maybe, to match 'X86_FEATURE_HYPERVISOR' elsewhere in the
> Xen code?
>
> With that change, Acked-by: Tim Deegan<tim@xen.org>

New version with that change attached.

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>


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diff -r 0d092359d86f tools/libxl/libxl_cpuid.c
--- a/tools/libxl/libxl_cpuid.c	Wed Oct 26 10:32:36 2011 +0200
+++ b/tools/libxl/libxl_cpuid.c	Wed Nov 02 11:41:51 2011 +0100
@@ -92,6 +92,7 @@ int libxl_cpuid_parse_config(libxl_cpuid
         {"proccount",    0x00000001, NA, CPUID_REG_EBX, 16,  8},
         {"clflush",      0x00000001, NA, CPUID_REG_EBX,  8,  8},
         {"brandid",      0x00000001, NA, CPUID_REG_EBX,  0,  8},
+        {"hypervisor",   0x00000001, NA, CPUID_REG_ECX, 31,  1},
         {"f16c",         0x00000001, NA, CPUID_REG_ECX, 29,  1},
         {"avx",          0x00000001, NA, CPUID_REG_ECX, 28,  1},
         {"osxsave",      0x00000001, NA, CPUID_REG_ECX, 27,  1},
@@ -178,6 +179,13 @@ int libxl_cpuid_parse_config(libxl_cpuid
         {"procpkg",      0x00000004,  0, CPUID_REG_EAX, 26,  6},
         {"apicidsize",   0x80000008, NA, CPUID_REG_ECX, 12,  4},
         {"nc",           0x80000008, NA, CPUID_REG_ECX,  0,  8},
+        {"svm_npt",      0x8000000a, NA, CPUID_REG_EDX,  0,  1},
+        {"svm_lbrv",     0x8000000a, NA, CPUID_REG_EDX,  1,  1},
+        {"svm_nrips",    0x8000000a, NA, CPUID_REG_EDX,  3,  1},
+        {"svm_tscrate",  0x8000000a, NA, CPUID_REG_EDX,  4,  1},
+        {"svm_vmcbclean",0x8000000a, NA, CPUID_REG_EDX,  5,  1},
+        {"svm_decode",   0x8000000a, NA, CPUID_REG_EDX,  7,  1},
+        {"svm_pausefilt",0x8000000a, NA, CPUID_REG_EDX, 10,  1},
 
         {NULL, 0, CPUID_REG_INV, 0, 0}
     };

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